CPE/EE 428/528 VLSI Design II – Intro to TestingHardware Testing and Design for TestabilityTesting vs. SimulationImportance of TestImportance of Test (cont’d)An Approach to TestingFaultsReliabilityReliability (cont’d)Testing Combinational LogicStuck-at FaultsStuck-at Faults for AND and OR gatesTesting an AND-OR NetworkPath Detection & Sensitization: Small ExampleAn ExampleAn Example (cont’d)Testing Sequential LogicTesting Sequential Logic (cont’d)Slide 19Slide 20Slide 21Scan TestingScan Path TestingSlide 24Scan Path Testing: An ExampleScan ChainScan Test with Multiple ICsBoundary ScanBoundary Scan RegisterPCB with Boundary Scan ICsBoundary Scan CellBasic Boundary Scan ArchitectureTAP ControllerTAP Controller: How it Works (I)Instructions in the IEEE StandardInterconnection Testing using Boundary ScanSteps Required to Test ConnectionsSteps Required to Test Connections (cont’d)Slide 39Slide 40Slide 41Built-In Self-TestSelf-Test Circuit for RAMLinear Feedback Shift Registers (LFSR)Self-Test Circuit for RAM with Signature RegsCPE/EE 428/528VLSI Design II – Intro to TestingElectrical and Computer EngineeringUniversity of Alabama in Huntsville01/14/19 UAHAM 2Hardware Testing and Design for Testability•Testing during design process–use VHDL test benches to verify that the overall design and algorithms used are correct–verify timing and logic after the synthesis•Post-fabrication testing–when a digital system is manufactured,test to verify that it is free from manufacturing defects–today, cost of testing is major component of the manufacturing cost–efficient techniques are needed to test anddesign digital systems so that they are easy to test01/14/19 UAHAM 3Testing vs. Simulation•Distinction to be made–Simulation — determine if the design is correct•Not only is the design right, but is it the right design — all the validation before manufacturing •It meets a specification. For instance, it is a UART•Testing a design’s correctness is in the realm of simulationStick in a byte and see if the UART shifts it out correctly–Testing — determine if the manufactured item is correct•Given that the design was correct, was it manufactured correctly•Do any faults show up that keep the design from working correctly•This is generally the realm of testing01/14/19 UAHAM 4Importance of Test•Defect Level = measure of product quality–10 defective of 100,000 => defect level is 0.1%•Let’s consider an example–Company ABC makes an ASIC, the bASIC, and sells to company EDF, at 10$ each•100 000 shipped = $1 million–EDF assembles, e.g, PC motherboards and sells to GHI•Suppose that rejected PCBs due to defective bASIC incur an average $200 board repair cost•Total repair cost for 5% bASIC defect level is 5000*200 = $ 1 million (?)–GHI sells bPC computers for $5,000, with profit of $500 each•Suppose that 10% of PCBs that contain defective bASIC that past the chip test, manage to pass the PCB test•Suppose that the cost of repairing or replacing system is $10,00001/14/19 UAHAM 5Importance of Test (cont’d)•Defect levels in PCBs•Defect levels in systemsASIC defect level Defective ASICs Total PCB repair cost5% 5000 $1 million1% 1000 $200,0000.1% 100 $20,0000.01% 10 $2,000ASIC defect level Defective ASICs Defective boards Total repair cost5% 5000 500 $5 million1% 1000 100 $1 million0.1% 100 10 $100,0000.01% 10 1 $10,00001/14/19 UAHAM 6An Approach to Testing•Problem: how to figure out, systematically, whether the whole thing works–It is simple, just try all combinations of inputs–Let’s see, n = 25 inputs, and m = 50 states — that’s 2n+m tests. At 10 ns per test, that’s ………10 million years.–So, how do you determine a subset of inputs to try and be assured that, say, 99% of all faults will be detected?01/14/19 UAHAM 7Faults•What are they? Where do they come from?•Any problem during manufacturing may introduce a defect that in turn may introduce a fault•Fabrication: hundreds processing steps–defects often occur in metallization •e.g., shorts due to underetching, opens or breaks due to overetching•After fabrication–may occur during wafer probing, wafer saw, die attach, wire bonding => each of these steps have their own defect and failure mechanism01/14/19 UAHAM 8Reliability•Defects may be nonfatal, but they may cause failures early in the life of a product => infant mortality•Failures as a function of life–typically the trend is described with bathtub curve•the failure rates decrease rapidly to a low value•than, it remains the steady until the end of life,•when failure rates increase again•Elevated temperature, current, or voltage may also accelerate failures•Reliability –measured using the Mean Time Between Failures (MTBF) for repairable products, or–using the Mean Time To Failure (MTTF) for a fatal failure–Failure In Time (FIT): 1 FIT = a single failure in 109 hours01/14/19 UAHAM 9Reliability (cont’d)•Using FIT–sum the FITs of all components in a product in order to determine an overall measure for the product reliability•An example–Assumptions•Processor (standard part) 5 FITs•100 TTL pats, 50 at 10 FITs, 50 at 15 FITs•100 RAM chips, 6 FITs–Overall FIT: 5 + 50x10 + 50x15 + 100x6 = 1855•Reduce component count–Assumptions•Processor (custom) 7 FITs•9 ASICs, 10 FITs•5 SIMMs, 15 FITs–Overall FIT: 7 + 9x10 + 5x15 = 17501/14/19 UAHAM 10Testing Combinational Logic•Common types of errors–short circuit–open circuit•If the input to a gate is shorted to ground,the input acts as if it is stuck at logic 0–s-a-0 (stuck-at-0) faults•If the input to a gate is shorted to positive supply voltage, the input acts as if it is stuck at logic 1–s-a-1 (stuck-at-1) faults01/14/19 UAHAM 11Stuck-at Faults•How many single stuck-at faults —–2 (n + 1) — where n is the number of inputs•We will assume –that there is only one stuck-at-fault active at a time in the whole circuit–“SSF” — single stuck-at faults-a-0s-a-0s-a-0s-a-1s-a-1s-a-101/14/19 UAHAM 12Stuck-at Faults for AND and OR gatesTest a for s-a-0Test a for s-a-1Test a for s-a-1Test a for s-a-001/14/19 UAHAM 13Testing an AND-OR NetworkBRUTE-FORCE testing:apply 29=512 different input combinations and check the output01/14/19 UAHAM 14Path Detection & Sensitization: Small ExampleTest n to s-a-1We can test a, m, n, or p to s-a-0n=0 =>m=0, c = 0 =>a=0, b=1, c=0d=1,