CPE/EE 428, CPE 528: Session #13Programmable InterconnectActel Programmable InterconnectSlide 4Detail of ACT1 Channel ArchitectureRouting ResourcesElmore’s ConstantRC Delay in Antifuse ConnectionsRC Delay in Antifuse Connections (cont’d)Xilinx LCA InterconnectXilinx LCA Interconnect (cont.)Xilinx Switching Matrix and Components of Interconnect DelayXilinx EPLD InterconnectAltera MAX 5000 and 7000 InterconnectAltera MAX 9000 Interconnect ArchitectureAltera FlexSummaryCPE/EE 428, CPE 528 Programmable ASIC IO CellsI/O RequirementsMotor Control (Robotic Arm) ApplicationCMOS Output BufferI/O Circuit for High Current Motor ControlTotem-Pole OutputAC Output3 State Bus Example3 State Bus TimingCharacterizing AC Output PadsSupply (GND) BounceTransmission LinesTransmission Line ExampleTerminating a Transmission LineTerminating a Transmission Line (cont.)DC Input - Switch BounceDebouncing Using HysteresisNoise Margins - Another RepresentationNoise Margins - Interfacing TTL and CMOSNoise Margins - Mixed Voltage Systems (e.g. 3.3V and 5V)Metastability ExampleProbability of UpsetProbability of Upset ExampleConstants tc, T0MTBF as a Function of Resolution TimeClock InputClock Input ExampleProgrammable Input Delay to Eliminate Hold Time on Data InputsEffect of Clock Latency on Registered OutputsPower InputPower DissipationPower Dissipation (cont’d)Example FPGA I/O BlockExample FPGA I/O Block: XC4000Timing Model with I/O BlockExample FPGA I/O Block (cont.)Slide 54Slide 55CPE/EE 428, CPE 528: Session #13Department of Electrical and Computer Engineering University of Alabama in Huntsville01/15/19 VLSI Design II: VHDL 2Programmable Interconnect•In addition to programmable cells, programmable ASICs must have programmable interconnect to connect cells together to form logic function•Structure and complexity of the interconnect is determined primarily by the programming technology and architecture of the basic cell•Interconnect is typically done on aluminum-based metal layers–Resistance of approximately 50 m/square–Line capacitance of approximately 0.2 pF/cm•Early programmable ASICs had two metal interconnect layers, but current, high density parts may have three or more metal layers01/15/19 VLSI Design II: VHDL 3Actel Programmable Interconnect•Actel interconnect is similar to a channeled gate array–Horizontal routing channels between rows of logic modules–Vertical routing channels on top of cells•Each channel has a fixed number of tracks each of which holds one wire•Wires in track are divided into segments of various lengths - segmented channel routing•Long vertical tracks (LVT) extend the entire height of the chip•Each logic module has connections to its inputs and outputs called stubs–Input stubs extend vertically into routing channels above and below logic module–Output stub extends vertically 2 channels up and 2 channels down•Wires are connected by antifuses01/15/19 VLSI Design II: VHDL 4Actel Programmable InterconnectFigure 7.1 The interconnect architecture used in an Actel ACT family FPGA.01/15/19 VLSI Design II: VHDL 5Detail of ACT1 Channel ArchitectureFigure 7.2 ACT 1 horizontal and vertical channel architecture.01/15/19 VLSI Design II: VHDL 6Routing Resources•ACT 1 interconnection architecture–22 horizontal tracks per channel for signal routing with3 dedicated for VDD, GND, GCLK–8 vertical tracks per LM are available for inputs (4 from the LM above the channel, 4 from the LM below) – input stub–4 vertical tracks per LM for outputs – output stub•a vertical track extends across the two channels above the module and the two channels below –1 long vertical track (spans the entire height of the chip)01/15/19 VLSI Design II: VHDL 7Elmore’s Constant•Approximation of waveform at node i:where Rki is the resistance of the path to V0 shared by node k and node i•Examples: R24 = R1, R22 = R1+R2, and R31 = R1•If the switching points are assumed to be at the 0.35 and 0.65 points, the delay at node i can be approximated by DIFigure 7.3 Measuring the delay of a net. (a) An RC tree. (b) The waveforms as a result of closing the switch at t=0. nkkkiDitiCRetVDi1;01/15/19 VLSI Design II: VHDL 8RC Delay in Antifuse ConnectionsFigure 7.4 Actel routing model. (a) A four-antifuse connection. L0 is an output stub, L1 and L3 are horizontal tracks, L2 is a long vertical track (LVT), and L4 is an input stub. (b) An RC-tree model. Each antifuse is modeled by a resistance and each interconnect segment is modeled by a capacitance.01/15/19 VLSI Design II: VHDL 9RC Delay in Antifuse Connections (cont’d)•Rn - resistance of antifuse, Cn - capacitance of wire segmentD4 = R14C1 + R24C2 + R34C3 + R44C4 = (R1 + R2 + R3 + R4)C4 + (R1 + R2 + R3)C3 + (R1 + R2)C2 + R1C1•If all antifuse resistances are approximately equal and much larger than the resistance of the wire segment, then: R1 = R2 = R3 = R4, and:D4 = 4RC4 + 3RC3 + 2RC2 + RC1•A connection with two antifuses will generate a 3RC time constant, a connection with three antifuses will generate a 6RC time constant, and a connection with 4 antifuses will generate a 10RC time constant•Interconnect delay grows quadratically ( n2) as the number of antifuses n increases01/15/19 VLSI Design II: VHDL 10Xilinx LCA Interconnect•Xilinx LCA interconnect has a hierarchical architecture:–Vertical lines and horizontal lines run between CLBs–General-purpose interconnect joins switch boxes (also known as magic boxes or switching matrices)–Long lines run across the entire chip - can be used to form internal buses using the three-state buffers that are next to each CLB–Direct connections bypass the switch matrices and directly connect adjacent CLBs–Programmable Interconnect Points (PIPs) are programmable pass transistors the connect CLB inputs and outputs to the routing network–Bi-directional interconnect buffers (BIDI) restore the logic level and logic strength on long interconnect paths01/15/19 VLSI Design II: VHDL 11Xilinx LCA Interconnect (cont.)Figure 7.5 Xilinx LCA interconnect. (a) The LCA architecture (notice the matrix element size is larger than a CLB). (b) A simplified representation of the interconnect resources. Each of the lines is a bus.01/15/19 VLSI Design II: VHDL 12Xilinx Switching Matrix and Components of Interconnect DelayFigure 7.6 Components of interconnect delay in a Xilinx LCA array. (a) A portion of the interconnect around the CLBs. (b)