CPE/EE 428, CPE 528 Basic VHDLLecture GoalsOutlineModule Outline (Cont.)Slide 5Reasons for Using VHDLVHDL’s HistoryVHDL’s History (Cont.)Gajski and Kuhn’s Y ChartAdditional Benefits of VHDLPutting It All TogetherModule OutlineVHDL Design ExampleVHDL Design Example Entity DeclarationVHDL Design Example Behavioral SpecificationVHDL Design Example Data Flow SpecificationVHDL Design Example Structural SpecificationVHDL Design Example Structural Specification (Cont.)VHDL Design Example Structural Specification (cont.)Slide 20VHDL Model ComponentsVHDL Model Components (cont.)Entity DeclarationsEntity Declarations Port ClauseEntity Declarations Port Clause (cont.)Entity Declarations Generic ClauseArchitecture BodiesStructural DescriptionsBehavioral DescriptionsTiming ModelDelay TypesTransport DelayInertial DelayInertial Delay (cont.)Delta DelayDelta Delay An Example without Delta DelayDelta Delay An Example with Delta DelaySlide 38Data TypesVHDL Data Types Scalar TypesVHDL Data Types Scalar Types (Cont.)Slide 42Slide 43VHDL Data Types Composite TypesVHDL Data Types Composite Types (Cont.)Slide 46VHDL Data Types Access TypeVHDL Data Types SubtypesVHDL Data Types SummaryVHDL ObjectsVHDL Objects ConstantsVHDL Objects VariablesVHDL Objects SignalsSignals and VariablesVHDL Objects Signals vs VariablesVHDL Objects Signals vs Variables (Cont.)VHDL Objects FilesSimulation Cycle Revisited Sequential vs Concurrent StatementsConcurrent StatementsSequential StatementsPackages and LibrariesPackagesPackages DeclarationPackages Package BodyPackages Use ClauseLibrariesAttributesAttributes Register ExampleAttributes Register Example (Cont.)Attributes Register Example (Cont.)OperatorsOperators ExamplesSlide 73ExamplesGlobal PackageTwo Input AND Gate ExampleAnd Gate Simulation ResultsTri-State Buffer ExampleTri-State Buffer Simulation ResultsD Flip Flop ExampleD Flip Flop Simulation ResultsSlide 82SummarySlide 84CPE/EE 428, CPE 528 Basic VHDL Department of Electrical and Computer Engineering University of Alabama in Huntsville14/01/19 ECE-UAH: VLSI Design II 2Lecture GoalsIntroduce basic VHDL constructs Introduce the VHDL simulation cycle and timing modelIllustrate VHDL’s utility as a digital hardware description language14/01/19 ECE-UAH: VLSI Design II 3OutlineIntroductionVHDL Design Example VHDL Model ComponentsEntity DeclarationsArchitecture DescriptionsTiming Model14/01/19 ECE-UAH: VLSI Design II 4Module Outline (Cont.)Basic VHDL ConstructsData typesObjectsSequential and concurrent statementsPackages and librariesAttributesPredefined operatorsExamplesSummary14/01/19 ECE-UAH: VLSI Design II 5OutlineIntroductionVHDL Design ExampleVHDL Model ComponentsBasic VHDL ConstructsExamplesSummary14/01/19 ECE-UAH: VLSI Design II 6Reasons for Using VHDLVHDL is an international IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwideVHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language VHDL enables hardware modeling from the gate to system levelVHDL provides a mechanism for digital design and reusable design documentation14/01/19 ECE-UAH: VLSI Design II 7VHDL’s HistoryVery High Speed Integrated Circuit (VHSIC) ProgramLaunched in 1980Aggressive effort to advance state of the artObject was to achieve significant gains in VLSI technologyNeed for common descriptive language$17 Million for direct VHDL development$16 Million for VHDL design toolsWoods Hole WorkshopHeld in June 1981 in MassachusettsDiscussion of VHSIC goalsComprised of members of industry, government, and academia14/01/19 ECE-UAH: VLSI Design II 8VHDL’s History (Cont.)In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDLIn August 1985, the final version of the language under government contract was released: VHDL Version 7.2In December 1987, VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standardIn September 1993, VHDL was restandardized to clarify and enhance the language14/01/19 ECE-UAH: VLSI Design II 9Gajski and Kuhn’s Y ChartPhysical/GeometryStructuralBehavioralProcessorHardware ModulesALUs, RegistersGates, FFsTransistorsSystemsAlgorithmsRegister TransferLogicTransfer FunctionsArchitecturalAlgorithmicFunctional BlockLogicCircuitRectanglesCell, Module PlansFloor PlansClustersPhysical Partitions14/01/19 ECE-UAH: VLSI Design II 10Additional Benefits of VHDLAllows for various design methodologiesProvides technology independenceDescribes a wide variety of digital hardwareEases communication through standard languageAllows for better design managementProvides a flexible design languageHas given rise to derivative standards:WAVES, VITAL, Analog VHDL14/01/19 ECE-UAH: VLSI Design II 11Putting It All TogetherGenerics PortsEntityArchitectureArchitectureArchitectureConcurrentStatementsProcessSequential StatementsConcurrentStatementsPackage14/01/19 ECE-UAH: VLSI Design II 12Module OutlineIntroductionVHDL Design ExampleVHDL Models of HardwareBasic VHDL ConstructsExamplesSummary14/01/19 ECE-UAH: VLSI Design II 13VHDL Design ExampleProblem: Design a single bit half adder with carry and enableSpecificationsInputs and outputs are each one bitWhen enable is high, result gets x plus yWhen enable is high, carry gets any carry of x plus yOutputs are zero when enable input is lowxyenablecarryresultHalf Adder14/01/19 ECE-UAH: VLSI Design II 14VHDL Design Example Entity DeclarationAs a first step, the entity declaration describes the interface of the componentinput and output ports are declaredxyenablecarryresultHalfAdderENTITY half_adder ISPORT( x, y, enable: IN BIT; carry, result: OUT BIT);END half_adder;14/01/19 ECE-UAH: VLSI Design II 15VHDL Design ExampleBehavioral Specification A high level description can be used to describe the function of the adderThe model can then be simulated to verify correct functionality of the componentARCHITECTURE half_adder_a OF half_adder ISBEGINPROCESS (x, y, enable)BEGINIF enable = ‘1’ THENresult <= x XOR y;carry <= x AND y;ELSEcarry <= ‘0’;result <= ‘0’;END IF;END PROCESS;END half_adder_a;14/01/19 ECE-UAH: VLSI Design II 16VHDL Design ExampleData Flow SpecificationA second method is to use logic equations to develop a data flow descriptionAgain,