•1CPE/EE 428/528VLSI Design II – Intro to Testing(Part 3)Electrical and Computer EngineeringUniversity of Alabama in Huntsville13/03/2003 UAHAM 2Scan Test with Multiple ICs13/03/2003 UAHAM 3Boundary Scan• PCB testing has become more difficult– ICs have become more complex, with more and more pins – PCBs have become more denser with multiple layers and fine traces– Bed-of-nails testing• use sharp probes to contact the traces on the board• test data are applied to and read from various ICs • => not practical for high-density PCBs with fine traces and complex ICs• Boundary scan test methodology:introduced to facilitate the testing of complex PC boards– developed by JTAG (Joint Task Action Group) – adopted as ANSI/IEEE Standard 1149.1 –“Standard Test Access Port and Boundary Scan Architecture”– IC manufacturers make ICs that conform the standard– ICs can be linked together on a PCB, so that they can be tested using only a few pins on the PCB edge connector13/03/2003 UAHAM 4Boundary Scan Register• Boundary Scan Register (BSR) – cells of the BSR are placed between input or output pins and the internal core logic• Four or five pins of the IC are devoted to the test-access-port (TAP)TAP pinsBoundary scan cells• TDI – Test data input (data are shifted serially into the BSR)• TCK – Test clock• TMS – Test mode select• TDO – Test data output (serial output from BSR)• TRST – Test reset (resets the TAP controller and test logic –optional pin)•213/03/2003 UAHAM 5PCB with Boundary Scan ICs• BSRs in the ICs are linked together serially in a single chain with input TDI and output TDO. • TCK, TMS, TRST are connected in parallel to all of the ICs.13/03/2003 UAHAM 6Boundary Scan Cell Capture FFUpdate FF13/03/2003 UAHAM 7Basic Boundary Scan Architecture• BSR1 – shift register, which consists of the Q1 flip-flops in the boundary scan cells• BSR2 – represents the Q2 flip-flops; can be parallel loaded from BSR1 when an update signal is received• TDI can be shifted into the BSR1, through a bypass register, or into the ISR13/03/2003 UAHAM 8TAP ControllerTMS is inputAffect ASIC core•313/03/2003 UAHAM 9TAP Controller: How it Works (I)• TAP Controller – 16 state FSM – Change states depending on TMS and TCK– Output: signals to control the test data registers and instruction register (including serial shift clocks and update clocks)• Test-logic-reset is the initial state; on a low TMS go to Run-Test/Idle state• TMS: 1100 => Shift-IR • In Shift-IR command is shifted in through TDI port• …13/03/2003 UAHAM 10Instructions in the IEEE Standard• BYPASS: allows the TDI serial data to go trough 1-bit bypass register on the IC instead of through the BSR1. In this way one or more ICs on the PCB may be bypassed.• SAMPE/RELOAD: used to scan the BSR without interfering with the normal operation of the core logic. Data is transferred to or from the core logic from or to the IC pins without interference. Samples of this data can be taken and scanned out through the BSR. Test data can be shifted into the BSR. • EXTEST: allows board-level interconnect testing and testing of clusters of components which do not incorporate the boundary scan test features. Test data is shifted into the BSR and then it goes to the output pins. Data from the input pins is captured by the BSR.• INTEST (optional): this instruction allows testing of the core logic by shifting test data into the boundary-scan register. Data shifted into the BSR takes the place of data from the input pins, and output data from the core logic is loaded into the BSR.• RUNBIST (optional): this instruction causes special built-in self-test (BIST) logic within the IC to execute.13/03/2003 UAHAM 11Interconnection Testing using Boundary Scan• Test the connections between two ICs.• IC1: 2 input pins, 2 output pins.• IC2: 2 input pins, 2 output pins.• Test data is shifted into the BSRs via TDI.• Data from the input pins is parallel-loaded into the BSRs and shifted out via TDO.Assume:IR on each IC is 3 bits long with EXTEST coded as 000SAMPLE/PRELOAD as 001Test PC board traces between IC1 and IC213/03/2003 UAHAM 12Steps Required to Test Connections• 1. Reset the TAP state machine to the Test-Logic-Reset state by inputting a sequence of five 1's on TMS. The TAP controller is designed so that a sequence of five 1's will always reset it regardless of the present state. Alternatively, TRST could be asserted if it is available.• 2. Scan in the SAMPLE/PRELOAD instruction to both ICs using the sequences for TMS and TDI given below. – State: 0 1 2 9 10 11 11 11 11 11 11 12 15 2TMS: 0 1 1 0 0 0 0 0 0 0 1 1 1TDI: – – – – – 1 0 0 1 0 0 – –• The TMS sequence 01100 takes the TAP controller to the Shift-IR state. In this state, copies of the SAMPLE/PRELOAD instruction (code 001) are shifted into the instruction registers on both ICs. In the Update-IR state, the instructions are loaded into the instruction decode registers. Then the TAP controller goes back to the Select DR-scan state.•413/03/2003 UAHAM 13Steps Required to Test Connections (cont’d)• 3. Preload the first set of test data into the ICs using the sequences for TMS and TDI given below.State: 2 3 4 4 4 4 4 4 4 4 5 8 2TMS: 0 0 0 0 0 0 0 0 0 1 1 1TDI: – –0 1 0 0 0 1 0 0 ––Data is shifted into BSR1 in the Shift-DR state, and it is transferred to BSR2 in the Update-DR state. The result is as follows:13/03/2003 UAHAM 14Steps Required to Test Connections (cont’d)• 4. Scan in the EXTEST instruction to both ICs using the following sequences:State: 2 9 10 11 11 11 11 11 11 12 15 2TMS: 1 0 0 0 0 0 0 0 1 1 1TDI: – – – 0 0 0 0 0 0 – –The EXTEST instruction (000) is scanned into the instruction register in state Shift-IR and loaded into the instruction decode register in state Update-IR. At this point, the preloaded test data goes to the output pins, and it is transmitted to the adjacent IC input pins via the printed circuit board traces.13/03/2003 UAHAM 15Steps Required to Test Connections (cont’d)• 5. Capture the test results from the IC inputs. Scan this data out to TDO and scan the second set of test data in using the following sequences:State: 2 3 4 4 4 4 4 4 4 4 5 8 2TMS: 0 0 0 0 0 0 0 0 0 1 1 1TDI: – – 1 0 0 0 1 0 0 0 – –TDO: – – x x 1 0 x x 1 0 –