CPE 528: Lecture #5OutlineIEEE 1164 Standard LogicResolution Function for IEEE 9-valuedAND Table for IEEE 9-valuedAND Function for std_logic_vectorsGenericsRise/Fall Time Modeling Using GenericsGenerate Statements4-bit Adder4-bit Adder using GenerateWait StatementsForms of Wait StatementsMUX 16/1 ModelsMUX Models (cont’d)Slide 16Slide 17Assert StatementWriting Test Benches - MUX 16:1Writing Test Benches (cont’d)Slide 21D-FFsLatches4-bit Register4-bit Unsigned Up CounterGeneral Form of a Sequential NetworkSlide 27An ExampleVHDL ModelVHDL Model (cont’d)VHDL Model – Alternative StyleVHDL Model – Alternative Style (cont’d)CPE 528: Lecture #5 Department of Electrical and Computer Engineering University of Alabama in Huntsville14/01/19 UAH-CPE528 2OutlineReview: IEEE 1164 Standard LogicGenericsGenerate StatementsWait StatementCombinational Network ModelsWriting Test-benchesSequential Network Models14/01/19 UAH-CPE528 3IEEE 1164 Standard Logic9-valued logic system‘U’ – Uninitialized‘X’ – Forcing Unknown‘0’ – Forcing 0‘1’ – Forcing 1‘Z’ – High impedance‘W’ – Weak unknown‘L’ – Weak 0‘H’ – Weak 1‘-’ – Don’t careIf forcing and weak signal are tied together, the forcing signal dominates. Useful in modeling the internal operation of certain types of ICs.14/01/19 UAH-CPE528 4Resolution Function for IEEE 9-valued14/01/19 UAH-CPE528 5AND Table for IEEE 9-valued14/01/19 UAH-CPE528 6AND Function for std_logic_vectors14/01/19 UAH-CPE528 7GenericsUsed to specify parameters for a component in such a way that the parameter values must be specified when the component is instantiated Example: rise/fall time modeling14/01/19 UAH-CPE528 8Rise/Fall Time Modeling Using Generics14/01/19 UAH-CPE528 9Generate StatementsProvides an easy way of instantiating components when we have an iterative array of identical componentsExample: 4-bit RCA14/01/19 UAH-CPE528 104-bit Adder14/01/19 UAH-CPE528 114-bit Adder using Generate14/01/19 UAH-CPE528 12Wait Statements... an alternative to a sensitivity listNote: a process cannot have both wait statement(s)and a sensitivity listGeneric form of a process with wait statement(s)processbeginsequential-statementswait statementsequential-statementswait-statement...end process;How wait statements work?•Execute seq. statement until a wait statement is encountered.•Wait until the specified condition is satisfied.•Then execute the next set of sequential statements until the next wait statement is encountered.•...•When the end of the process is reached start over again at the beginning.14/01/19 UAH-CPE528 13Forms of Wait StatementsWait on until one of the signals in the sensitivity list changesWait forwaits until the time specified by the time expression has elapsedWhat is this:wait for 0 ns;Wait untilthe boolean expression is evaluated whenever one of the signals in the expression changes, and the process continues execution when the expression evaluates to TRUEwait on sensitivity-list;wait for time-expression;wait until boolean-expression;14/01/19 UAH-CPE528 14MUX 16/1 Modelslibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL1 of SELECTOR isbegin p0 : process (A, SEL) begin if (SEL = "0000") then Y <= A(0); elsif (SEL = "0001") then Y <= A(1); elsif (SEL = "0010") then Y <= A(2); elsif (SEL = "0011") then Y <= A(3); elsif (SEL = "0100") then Y <= A(4); elsif (SEL = "0101") then Y <= A(5); elsif (SEL = "0110") then Y <= A(6); elsif (SEL = "0111") then Y <= A(7); elsif (SEL = "1000") then Y <= A(8); elsif (SEL = "1001") then Y <= A(9); elsif (SEL = "1010") then Y <= A(10); elsif (SEL = "1011") then Y <= A(11); elsif (SEL = "1100") then Y <= A(12); elsif (SEL = "1101") then Y <= A(13); elsif (SEL = "1110") then Y <= A(14); else Y <= A(15); end if; end process;end RTL1;14/01/19 UAH-CPE528 15MUX Models (cont’d)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL3 of SELECTOR isbegin with SEL select Y <= A(0) when "0000", A(1) when "0001", A(2) when "0010", A(3) when "0011", A(4) when "0100", A(5) when "0101", A(6) when "0110", A(7) when "0111", A(8) when "1000", A(9) when "1001", A(10) when "1010", A(11) when "1011", A(12) when "1100", A(13) when "1101", A(14) when "1110", A(15) when others; end RTL3;14/01/19 UAH-CPE528 16MUX Models (cont’d)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL2 of SELECTOR isbegin p1 : process (A, SEL) begin case SEL is when "0000" => Y <= A(0); when "0001" => Y <= A(1); when "0010" => Y <= A(2); when "0011" => Y <= A(3); when "0100" => Y <= A(4); when "0101" => Y <= A(5); when "0110" => Y <= A(6); when "0111" => Y <= A(7); when "1000" => Y <= A(8); when "1001" => Y <= A(9); when "1010" => Y <= A(10); when "1011" => Y <= A(11); when "1100" => Y <= A(12); when "1101" => Y <= A(13); when "1110" => Y <= A(14); when others => Y <= A(15); end case; end process;end RTL2;14/01/19 UAH-CPE528 17MUX Models (cont’d)library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;entity SELECTOR is port ( A : in std_logic_vector(15 downto 0); SEL : in std_logic_vector( 3 downto 0); Y : out std_logic);end SELECTOR;architecture RTL4 of SELECTOR isbegin Y <= A(conv_integer(SEL));end RTL4;14/01/19 UAH-CPE528 18Assert StatementChecks to see if a certain condition is true,and if not causes an (error) message to be displayedFour possible severity levelsNOTEWARNINGERRORFAILUREAction taken for a severity level depends on the simulatorassert boolean-expressionreport string-expressionseverity severity-level;14/01/19 UAH-CPE528 19Writing Test Benches -