CPE 528: Lecture #4OutlineVHDL OperatorsExample of VHDL OperatorsExample of Shift OperatorsVHDL FunctionsFor LoopsAdd FunctionVHDL ProceduresProcedure for Adding Bit_vectorsParameters for Subprogram CallsReview: Operator OverloadingVHDL Package with Overloaded OperatorsMultivalued LogicTristate BuffersSignal ResolutionSignal Resolution (cont’d)Resolution Function for X01ZAND and OR Functions Using X01ZIEEE 1164 Standard LogicResolution Function for IEEE 9-valuedAND Table for IEEE 9-valuedAND Function for std_logic_vectorsGenericsRise/Fall Time Modeling Using GenericsGenerate Statements4-bit Adder4-bit Adder using GenerateCPE 528: Lecture #4 Department of Electrical and Computer Engineering University of Alabama in Huntsville14/01/19 UAH-CPE528 2OutlineVHDL operatorsFunctions and ProceduresOperator OverloadingMultivalued Logic and Signal ResolutionIEEE 1164 Standard LogicGenericsGenerate Statements14/01/19 UAH-CPE528 3VHDL Operators1. Binary logical operators: and or nand nor xor xnor2. Relational: = /= < <= > >=3. Shift: sll srl sla sra rol ror4. Adding: + - & (concatenation)5. Unary sign: + -6. Multiplying: * / mod rem7. Miscellaneous: not abs **•Class 7 has the highest precedence (applied first),followed by class 6, then class 5, etc14/01/19 UAH-CPE528 4Example of VHDL Operators14/01/19 UAH-CPE528 5Example of Shift Operators14/01/19 UAH-CPE528 6VHDL FunctionsFunctions execute a sequential algorithm and return a single value to calling program •A = “10010101”•General form14/01/19 UAH-CPE528 7For Loops14/01/19 UAH-CPE528 8Add Function14/01/19 UAH-CPE528 9VHDL ProceduresFacilitate decomposition of VHDL code into modulesProcedures can return any number of values using output parametersprocedure_name (actual-parameter-list);•General formprocedure procedure_name (formal-parameter-list) is [declarations]beginSequential-statementsend procedure_name;14/01/19 UAH-CPE528 10Procedure for Adding Bit_vectors14/01/19 UAH-CPE528 11Parameters for Subprogram Calls14/01/19 UAH-CPE528 12Review: Operator OverloadingOperators +, - operate on integers Write procedures for bit vector addition/subtractionaddvec, subvecOperator overloading allows using + operator to implicitly call an appropriate addition functionHow does it work?When compiler encounters a function declaration in which the function name is an operator enclosed in double quotes, the compiler treats the function as an operator overloading (“+”)when a “+” operator is encountered, the compiler automatically checks the types of operands and calls appropriate functions14/01/19 UAH-CPE528 13VHDL Package with Overloaded Operators14/01/19 UAH-CPE528 14Multivalued LogicBit (0, 1)Tristate buffers and buses =>high impedance state ‘Z’Unknown state ‘X’ e. g., a gate is driven by ‘Z’, output is unknowna signal is simultaneously driven by ‘0’ and ‘1’14/01/19 UAH-CPE528 15Tristate BuffersResolution function to determine the actual value of f since it is driven from two different sources14/01/19 UAH-CPE528 16Signal ResolutionVHDL signals may either be resolved or unresolvedResolved signals have an associated resolution functionBit type is unresolved – there is no resolution functionif you drive a bit signal to two different values in two concurrent statements, the compiler will generate an error14/01/19 UAH-CPE528 17Signal Resolution (cont’d)signal R : X01Z := ‘Z’; ...R <= transport ‘0’ after 2 ns, ‘Z’ after 6 ns;R <= transport ‘1’ after 4 ns;R <= transport ‘1’ after 8 ns, ‘0’ after 10 ns;14/01/19 UAH-CPE528 18Resolution Function for X01ZDefine AND and OR for 4-valued inputs?14/01/19 UAH-CPE528 19AND and OR Functions Using X01ZAND ‘X’ ‘0’ ‘1’ ‘Z’‘X’ ‘X’ ‘0’ ‘X’ ‘X’‘0’ ‘0’ ‘0’ ‘0’ ‘0’‘1’ ‘X’ ‘0’ ‘1’ ‘X’‘Z’ ‘X’ ‘0’ ‘X’ ‘X’OR ‘X’ ‘0’ ‘1’ ‘Z’‘X’ ‘X’ ‘X’ ‘1’ ‘X’‘0’ ‘X’ ‘0’ ‘1’ ‘X’‘1’ ‘1’ ‘1’ ‘1’ ‘1’‘Z’ ‘X’ ‘X’ ‘1’ ‘X’14/01/19 UAH-CPE528 20IEEE 1164 Standard Logic9-valued logic system‘U’ – Uninitialized‘X’ – Forcing Unknown‘0’ – Forcing 0‘1’ – Forcing 1‘Z’ – High impedance‘W’ – Weak unknown‘L’ – Weak 0‘H’ – Weak 1‘-’ – Don’t careIf forcing and weak signal are tied together, the forcing signal dominates. Useful in modeling the internal operation of certain types of ICs.14/01/19 UAH-CPE528 21Resolution Function for IEEE 9-valued14/01/19 UAH-CPE528 22AND Table for IEEE 9-valued14/01/19 UAH-CPE528 23AND Function for std_logic_vectors14/01/19 UAH-CPE528 24GenericsUsed to specify parameters for a component in such a way that the parameter values must be specified when the component is instantiated Example: rise/fall time modeling14/01/19 UAH-CPE528 25Rise/Fall Time Modeling Using Generics14/01/19 UAH-CPE528 26Generate StatementsProvides an easy way of instantiating components when we have an iterative array of identical componentsExample: 4-bit RCA14/01/19 UAH-CPE528 274-bit Adder14/01/19 UAH-CPE528 284-bit Adder using