CPE 528: Session #12OutlineIntroductionActel ACTACTEL Act 1 Logic ModuleShannon Expansion TheoremAn ExampleMultiplexer Logic as Function GeneratorsMultiplexer Logic as Function Generators (cont’d)Slide 10Slide 11ACT 2 and ACT 3 Logic ModulesTiming Model and Critical PathWorst-case timingXilinx LCAXC3000 CLBXC3000 CLB (cont’d)Slide 18XC4000 Logic BlockSlide 20XC5200 Logic BlockXilinx CLB AnalysisAltera FLEX (8000)Altera MAXAltera MAX (cont’d)Slide 26Registered PALLogic ExpandersLogic Expander ImplementationLogic Expanders (cont’d)Altera MAX architectureTiming ModelSlide 33Slide 34Power Dissipation in Complex PLDsCPE 528: Session #12 Department of Electrical and Computer Engineering University of Alabama in Huntsville14/01/19 UAH-CPE528 2OutlineIntroductionActel Logic ModulesXilinx LCAAltera FLEX, Altera MAXPower Dissipation14/01/19 UAH-CPE528 3IntroductionBasic internal structurePLB – Programmable Logic Blocks PI – Programmable InterconnectTypes of basic logic cells(1) multiplexer based (2) look-up table based, and (3) programmable array logic14/01/19 UAH-CPE528 4Actel ACTActel ACT basic logic cell – Logic ModuleActel ACT 1 uses just one type of Logic ModuleActel ACT 2 and 3 use two different types of Logic Modules14/01/19 UAH-CPE528 5ACTEL Act 1 Logic Module(a)Organization of the basic logic cells. (b)The ACT1 Logic Module. (c)An implementation using pass transistors (without any buffering). (d)An example logic macro. (Source: Actel.)14/01/19 UAH-CPE528 6Shannon Expansion TheoremExpansionF = F · 1 = F · (A + A’)= F · A + F · A‘Example: expand F with respect to AF = A' · B + A · B · C' + A' · B' · C= A · (B · C') + A' · (B + B' · C)cofactor F wrt A = B · C‘, cofactor F wrt A’ = B + B' · CF with respect to BF = B · (A' + A · C') + B' · (A' · C)We can continue to expand a function until we reach the canonical form – a unique representation that uses only mintermsminterm is a product term that contains all the variables of F14/01/19 UAH-CPE528 7An ExampleF = (A · B) + (B' · C) + D= (A · B) + (B' · C) + [D ·(B + B’)]= B·(A+D) + B’·(C+D) = B·F2 + B’·F1F2 = A + D = A + D·(A + A’) = A + A’·D = A·1 + A’·DF1 = C + D = C + D·(C + C’) = C + C’·D = C·1 + C’·DImplementationA0 = D, A1 = 1, SA = C (F1)B0 = D, B1 = 1, SB = A (F2)S0 = 0, S1 = B14/01/19 UAH-CPE528 8Multiplexer Logic as Function GeneratorsLogic functions of 2 variables10 functions of these 16 can be implemented using just one 2:1 multiplexer(See Table 5.1 of the textbook)14/01/19 UAH-CPE528 9Multiplexer Logic as Function Generators (cont’d)Useful functionsINV. The MUX acts as an inverter for one input only. BUF. The MUX just passes one of the MUX inputs directly to the output. AND. A two-input AND. OR. A two-input OR. AND1-1. A two-input AND gate with inverted input, equivalent to an NOR-11. NOR1-1. A two-input NOR gate with inverted input, equivalent to an AND-11.14/01/19 UAH-CPE528 10Multiplexer Logic as Function Generators (cont’d)Figure 5.3 The ACT1 logic module as a boolean function generator. (a) A 2:1 MUX viewed as a logic wheel. (b) The ACT1 logic module viewed as two function wheels.14/01/19 UAH-CPE528 11An ExampleF = NAND(A, B)F = (A · B)’ = A’ + B' = A’ + B’·(A’ + A) = A’ + B’· A = 1·A’ + B’·AImplementationWheel 1 => 1 (A0 = 1, A1 = 1, SA = 1)Wheel 2 => B’ (B0 = 1, B1 = 0, SB = B)MUX (1, B’, A) => S0 = A, S1 = 0Note: We do not have to worry how to use Logic Modules to construct combinational logic functions – e.g., we use NAND2 gate symbol and software takes care of connecting the inputs in the right way to the Logic Module14/01/19 UAH-CPE528 12ACT 2 and ACT 3 Logic ModulesFigure 5.4 The ACT2 and ACT3 logic modules. (a) The C-module. (b) The ACT2 S-module. (c) The ACT3 S-module. (d) The equivalent circuit of the SE. (e) The SE configured as a positive edge-triggered D flip-flop.14/01/19 UAH-CPE528 13Timing Model and Critical PathExact delay values in Actel FPGAs can not be determined until interconnect delay is known – i.e., place and route are doneCritical path delay between registers is: tPD + tSUD + tCOThere is also a hold time for the flip-flops - tHThe combinational logic delay tPD is dependent on the logic function (which may take more than one LM) and the wiring delaysThe flip-flop output delay tCO can also be influenced by the number of gates it drives (fanout)14/01/19 UAH-CPE528 14Worst-case timingMax delays in CMOS occur whenoperating under minimum voltagemaximum temperatureslow-slow process conditions (process variation which results in slow p-channel and slow n-channel transistors)Electronic Equipment classesCommercial. VDD = 5 V ± 5 %, T A (ambient) = 0 to +70 °C. Industrial. VDD = 5 V ± 10 %, T A (ambient) = –40 to +85 °C. Military: VDD = 5 V ± 10 %, T C (case) = –55 to +125 °C. Military: Standard MIL-STD-883C Class B. Military extended: Unmanned spacecraft.Tj – junction temperature => temperature of the transistors on the chip to calculate this we need power dissipated and thermal properties of the package14/01/19 UAH-CPE528 15Xilinx LCAXilinix LCA (Logic Cell Array) Configurable Logic Blocks (CLBs) bigger and more complex than the Actel cells =>coarse-grain architectureXC3000 CLB inputsfive logic inputs (A-E)common clock input (K)asynchronous direct-reset input (RD)enable clock (EC)XC3000 CLB outputsX, YUsing programmable MUXes connected to the SRAM programming cells we can independently connect each of the two CLB outputs to the outputs of flip-flops (QX, QY) or to the output of the combinational logic (F, G)14/01/19 UAH-CPE528 16XC3000 CLBFigure 5.6 The Xilinx XC3000 CLB (configurable logic block).14/01/19 UAH-CPE528 17XC3000 CLB (cont’d)LUT – Look-Up Table32-bit LUT stored in 32 bits of SRAMSuppose we need to implement the function F,F = A·B·C·D·Eset the content of LUT cell number 31 to 1clear the content of all other LUT cells (0 – 30)apply the input variables as an address to the SRAMonly when ABCDE = ‘11111’ the output F will be ‘1’CLB propagation delay is fixed, equal to LUT access time and does not depend on the function implemented14/01/19 UAH-CPE528 18XC3000 CLB (cont’d)Combinational block