FPGA Advantage BookcaseGetting Started with FPGA Advantage TutorialTABLE OF CONTENTSAbout This ManualGetting Started with FPGA AdvantageWelcome to FPGA AdvantageInvoking FPGA AdvantageExploring the DesignsSet Default LanguageImport the Fibonacci DesignSelect Source HDL FilesConvert the Fibonacci DesignBrowsing the Fibonacci DesignExamine the State Machine Text ViewGenerate HDL for the State MachineCorrect the State Machine ErrorsCreate Graphical Test BenchSave the Test BenchSimulate Your DesignAdd Probes to the Test BenchAdd a BreakpointComplete the SimulationInvoke LeonardoSpectrumView the RTL SchematicFurther InformationEnd-User License AgreementGetting Started with FPGA Advantage TutorialSoftware Version 5.2 17 October 2001Copyright  Mentor Graphics Corporation 2000-2001.All rights reserved.This document contains information that is proprietary to Mentor Graphics Corporation. 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Boeckman Road, Wilsonville, Oregon 97070-7777.This is an unpublished work of Mentor Graphics Corporation.Web site: http://www.fpga-advantage.comEmail: [email protected] InformationGetting Started with FPGA Advantage Tutorial, Software Version 5.2i17 October 2001Trademark InformationThe following names which appear in this documentation set are trademarks, registered trademarks or service marks of Mentor Graphics Corporation:HDL Designer Series, HDL Designer, HDL Pilot, HDL Detective, HDL Author, HDL2Graphics, FPGA Advantage, Interconnect Table, Interface-Based Design, IBD, Inventra, LeonardoInsight, LeonardoSpectrum, Mentor, Mentor Graphics, ModelSim, ModuleWare, Renoir, Seamless, Seamless CVE and SpeedGate.The following names which appear in this documentation set are trademarks, registered trademarks or service marks of other companies:Adobe, the Adobe logo, Acrobat, the Acrobat logo, Exchange, FrameMaker and PostScript are registered trademarks of Adobe Systems Incorporated.Altera, APEX, MegaWizard and MAX+PLUS are registered trademarks and Quartus a trademark of Altera Corporation.ClearCase Attache is a trademark and ClearCase is a registered trademark of Rational Software Corporation.DesignSync is a registered trademark of Synchronicity Incorporated.FLEXlm is a trademark of Globetrotter Software, Incorporated.Hewlett-Packard (HP), HP-UX and PA-RISC are registered trademarks of Hewlett-Packard Company.Leapfrog, NC-Verilog, Verilog and Verilog-XL are trademarks and registered trademarks of Cadence Design Systems Incorporated.Netscape is a trademark of Netscape Communications Corporation.SPARC is a registered trademark and SPARCstation is a trademark of SPARC International Incorporated.SpyGlass is a trademark of Interra Inc.Sun Microsystems and Sun Workstation are registered trademarks of Sun Microsystems Incorporated. Sun and SunOS are trademarks of Sun Microsystems Incorporated.Synopsys, Design Analyzer, Design Compiler, FPGA Express, VCS, VCSi and VSS are trademarks of Synopsys Incorporated.Getting Started with FPGA Advantage Tutorial, Software Version 5.2iiTrademark Information17 October 2001Synplify is a registered trademark of Synplicity Incorporated.The Graphics Connection is a trademark of Square One.Visual SourceSafe and Windows are trademarks of Microsoft Corporation.UNIX is a registered trademark of UNIX System Laboratories, Incorporated.Xilinx is a registered trademark and Core Generator a trademark of Xilinx, Incorporated.Other brand or product names that appear in the documentation are trademarks or registered trademarks of their respective holders.Table of ContentsGetting Started with FPGA Advantage Tutorial, Software Version 5.2iii 17 October 2001About This Manual ................................................................................................ivGetting Started with FPGA Advantage.................................................................1Welcome to FPGA Advantage ...............................................................................1Invoking FPGA Advantage ....................................................................................2Exploring the Designs.............................................................................................4Set Default Language