CPE 528: Session #9OutlineVHDL Packages for Synthesis Base TypesVHDL Packages for Synthesis Base Types (cont.)Slide 5VHDL Packages for Synthesis Arithmetic PackagesIEEE Std 1076.3 Packages Numeric_BitSlide 8Slide 9IEEE Std 1076.3 Packages Numeric_StdSlide 11TypesTypes (cont.)AttributesConcurrent Signal Assignment StatementsConditional Signal Assignment StatementsSelected Signal Assignment StatementsOperatorsOperators (cont.)Slide 20Process StatementsProcess Statements ExampleProcess Statements Incomplete Sensitivity ListSequential Signal Assignment StatementsSequential IF StatementsSequential Case StatementsSequential Loop StatementsProcedures and FunctionsProcedures and Functions (cont.)Slide 30Using Procedures and FunctionsUsing Procedures and Functions (cont.)Tri-State LogicUse of Don’t Cares (‘X’s)After ClausesInferring LatchesAvioding LatchesProblems to Avoid Inferring Latches in Complex BehaviorsProblems to Avoid Synthesizing Asynchronous State Machines!Level Sensitive D LatchMaster-Slave D Latch (D Flip-Flop)Edge Sensitive D Flip-FlopEdge Sensitive D Flip-Flop (cont.)Edge Sensitive Flip-FlopsSlide 45Finite State Machine SynthesisMealy and Moore State Machine ModelsCPE 528: Session #9 Department of Electrical and Computer Engineering University of Alabama in Huntsville14/01/19 UAH-CPE528OutlineReview: VHDL Packages for SynthesisReview: VHDL for Combinational Logic SynthesisVHDL for Sequential Logic SynthesisVHDL for RTL Level SynthesisStructural VHDLImplementation Technology ConsiderationsSummary14/01/19 UAH-CPE528VHDL Packages for SynthesisBase TypesStandard bit types may be usedTypically IEEE 1164 Std. types are usedstd_ulogic typeValues ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for synthesis TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care );std_logic type - resolved std_ulogic typeUSE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_1164.ALL;14/01/19 UAH-CPE528VHDL Packages for SynthesisBase Types (cont.)The std_logic_1164 package also contains:Vectors of std_ulogic and std_logicSubtypes of std_logic - X01, X01Z, UX01, UX10ZLogic functions with various arguments - std_ulogic, std_logic, std_logic_vectorFUNCTION “and” (l,r : std_ulogic;) RETURN UX01;FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01;FUNCTION “or” (l,r : std_ulogic;) RETURN UX01;FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01;FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01;FUNCTION “xnor” (l,r : std_ulogic;) return ux01;FUNCTION "not" (l,r : std_ulogic) RETURN UX01;FUNCTION “and” (l,r : std_ulogic;) RETURN UX01;FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01;FUNCTION “or” (l,r : std_ulogic;) RETURN UX01;FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01;FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01;FUNCTION “xnor” (l,r : std_ulogic;) return ux01;FUNCTION "not" (l,r : std_ulogic) RETURN UX01;Conversion functionsFUNCTION To_bit(s:std_ulogic) RETURN bit;FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector;FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;FUNCTION To_bit(s:std_ulogic) RETURN bit;FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector;FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;14/01/19 UAH-CPE528VHDL Packages for SynthesisBase Types (cont.)Unknown functionsFUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean;FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean;FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean;FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean;Clock edge functionsFUNCTION Is_X (s:std_ulogic_vector) RETURN boolean;FUNCTION Is_X (s:std_logic_vector) RETURN boolean;FUNCTION Is_X (s:std_ulogic) RETURN boolean;FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean;FUNCTION Is_X (s:std_logic_vector) RETURN boolean;FUNCTION Is_X (s:std_ulogic) RETURN boolean;14/01/19 UAH-CPE528 6VHDL Packages for SynthesisArithmetic PackagesAll synthesis tools support some type of arithmetic packagesSynopsis developed packages based on std_logic_1164 package - supported by many other synthesis toolsstd_logic_arithstd_logic_signedstd_logic_unsignedActel synthesis tools support their own packageasyl.arithIEEE has developed standard packages for synthesis IEEE Std. 1076.3Numeric_BitNumeric_Std14/01/19 UAH-CPE528 7IEEE Std 1076.3 PackagesNumeric_Bit Type declarations for signed and unsigned numbersTYPE unsigned IS ARRAY (natural RANGE <> ) OF bit;TYPE signed IS ARRAY (natural RANGE <> ) OF bit;TYPE unsigned IS ARRAY (natural RANGE <> ) OF bit;TYPE signed IS ARRAY (natural RANGE <> ) OF bit;Arithmetic operators - various combinations of signed and unsigned argumentsFUNCTION “abs” (arg:unsigned) RETURN unsigned;FUNCTION “-” (arg:unsigned) RETURN unsigned;FUNCTION “+” (l,r:unsigned) RETURN unsigned;FUNCTION “-” (l,r:unsigned) RETURN unsigned;FUNCTION “*” (l,r:unsigned) RETURN unsigned;FUNCTION “/” (l,r:unsigned) RETURN unsigned;FUNCTION “rem” (l,r:unsigned) RETURN unsigned;FUNCTION “mod” (l,r:unsigned) RETURN unsigned;FUNCTION “abs” (arg:unsigned) RETURN unsigned;FUNCTION “-” (arg:unsigned) RETURN unsigned;FUNCTION “+” (l,r:unsigned) RETURN unsigned;FUNCTION “-” (l,r:unsigned) RETURN unsigned;FUNCTION “*” (l,r:unsigned) RETURN unsigned;FUNCTION “/” (l,r:unsigned) RETURN unsigned;FUNCTION “rem” (l,r:unsigned) RETURN unsigned;FUNCTION “mod” (l,r:unsigned) RETURN unsigned;USE IEEE.numeric_bit.ALL;USE IEEE.numeric_bit.ALL;14/01/19 UAH-CPE528 8IEEE Std 1076.3 PackagesNumeric_Bit Comparison operators - various combinations of signed and unsigned