CPE EE 428 528 VLSI Design II Intro to Testing Part 2 Electrical and Computer Engineering University of Alabama in Huntsville Testing Sequential Logic In general much more difficult than testing combinational logic since we must use sequences of inputs typically we can observe inputs and outputs not the state of flip flops assume the reset input so we can reset the network to the initial state Test procedure reset the network to the initial state apply a test sequence and observe the output sequence if the output is correct repeat the test for another sequence How many test sequences do we have how do we test that the initial state of the network under test is equivalent to the initial state of the correct network what is the sequence length 01 14 19 UAH AM 2 Testing Sequential Logic cont d In practice if the network has N or fewer states then apply only input sequences of length less than or equal 2N 1 Example consider a network which includes 5 inputs 1 output and 4 states total number of test sequences 25 7 235 infeasible derive a small set of test sequences that will adequately test a SN 01 14 19 UAH AM 3 Testing Sequential Logic cont d Consider input sequence X 010110011 Output sequence Z 001011110 If we change the network S3 S0 S3 S3 the output sequence will be the same Find distinguishing sequence an input sequence that will distinguish each state from the other states 01 14 19 UAH AM Input sequence X 11 S0 Z 01 S1 Z 11 S2 Z 10 S3 Z 00 4 Testing Sequential Logic cont d Verify each entry in the table using the following sequences 01 14 19 UAH AM 5 Testing Sequential Logic cont d Implementation of the FSM S0 00 S1 10 S2 01 S3 11 Test a for s a 1 to do this Q1Q2 must be 10 go to the state S1 and then set X to 0 R10 in normal operation the next state will be S0 if a is s a 1 then next state is S2 distinguish the state S0 or S2 apply sequence 11 Final sequence R1011 Normal output 0101 Faulty output 0110 01 14 19 UAH AM 6 Scan Testing Testing of sequential networks is greatly simplified if we can observe the state of all the flip flops instead of just observing the network outputs Connect the output of each flip flop to one of the IC pins Arrange flip flops to form a shift register shift out the state of flip flops bit by bit using a single serial output pin Scan path testing 01 14 19 UAH AM 7 Scan Path Testing Sequential network is separated into a combinational logic part and a state register composed of flip flops Two ports FFs 2 D inputs and 2 clock inputs D1 is stored in the FF on C1 pulse D2 is stored in the FF on C2 pulse Q of each FF is connected to D2 of the next FF to form a shift register 01 14 19 UAH AM 8 Scan Path Testing Normal operation system clock SCK C1 inputs X1X2 XN outputs Z1Z2 ZN Testing FFs are set to a specified state using the SDI and TCK test vector is applied X1X2 XN outputs Z1Z2 ZN are verified SCK is pulsed to take the network to the next state next state is verified by pulsing the TCK to shift the state code out of the scan register via SDO 01 14 19 UAH AM 9 Scan Path Testing An Example SQ X1X2 Q1Q2Q3 Z1Z2 01 14 19 UAH AM 10 Scan Chain 01 14 19 UAH AM 11 Scan Test with Multiple ICs 01 14 19 UAH AM 12 Boundary Scan PCB testing has become more difficult ICs have become more complex with more and more pins PCBs have become more denser with multiple layers and fine traces Bed of nails testing use sharp probes to contact the traces on the board test data are applied to and read from various ICs not practical for high density PCBs with fine traces and complex ICs Boundary scan test methodology introduced to facilitate the testing of complex PC boards developed by JTAG Joint Task Action Group adopted as ANSI IEEE Standard 1149 1 Standard Test Access Port and Boundary Scan Architecture IC manufacturers make ICs that conform the standard ICs can be linked together on a PCB so that they can be tested using only a few pins on the PCB edge connector 01 14 19 UAH AM 13 Boundary Scan Register Boundary Scan Register BSR cells of the BSR are placed between input or output pins and the internal core logic Four or five pins of the IC are devoted to the test access port TAP Boundary scan cells TAP pins TDI Test data input data are shifted serially into the BSR TCK Test clock TMS Test mode select TDO Test data output serial output from BSR TRST Test reset resets the TAP controller and test logic optional pin 01 14 19 UAH AM 14 PCB with Boundary Scan ICs BSRs in the ICs are linked together serially in a single chain with input TDI and output TDO TCK TMS TRST are connected in parallel to all of the ICs 01 14 19 UAH AM 15 Boundary Scan Cell Capture FF 01 14 19 Update FF UAH AM 16 Basic Boundary Scan Architecture BSR1 shift register which consists of the Q1 flip flops in the boundary scan cells BSR2 represents the Q2 flip flops can be parallel loaded from BSR1 when an update signal is received TDI can be shifted into the BSR1 through a bypass register or into the ISR 01 14 19 UAH AM 17 TAP Controller TMS is input Affect ASIC core 01 14 19 UAH AM 18 TAP Controller How it Works I TAP Controller 16 state FSM Change states depending on TMS and TCK Output signals to control the test data registers and instruction register including serial shift clocks and update clocks Test logic reset is the initial state on a low TMS go to Run Test Idle state TMS 1100 Shift IR In Shift IR command is shifted in through TDI port 01 14 19 UAH AM 19 Instructions in the IEEE Standard BYPASS allows the TDI serial data to go trough 1 bit bypass register on the IC instead of through the BSR1 In this way one or more ICs on the PCB may be bypassed SAMPE RELOAD used to scan the BSR without interfering with the normal operation of the core logic Data is transferred to or from the core logic from or to the IC pins without interference Samples of this data can be taken and scanned out through the BSR Test data can be shifted into the BSR EXTEST allows board level interconnect testing and testing of clusters of components which do not incorporate the boundary scan test features Test data is shifted into the BSR and then it goes to the output pins Data from the input pins is captured by the BSR INTEST optional …