UIC ECE 465 - Logic level sequential design (1 (10 pages)

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Logic level sequential design (1



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Logic level sequential design (1

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Pages:
10
School:
University of Illinois at Chicago
Course:
Ece 465 - Digital Systems Design

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ECE 465 7 1 Logic level sequential design 1 Logic level sequential design 1 Lecture 7 1 Goal This lecture is the former part of a group of 2 lectures split just for sake of manageability aiming at presenting the sequence of steps to be performed in the manual synthesis of sequential networks Paolo PRINETTO Politecnico di Torino Italy University of Illinois at Chicago IL USA Paolo Prinetto polito it Prinetto uic edu www testgroup polito it 7 1 Prerequisites Homework Modules 2 4 and 6 7 1 2 Students are invited to try to solve the proposed exercises by themselves before looking at the proposed solutions 3 7 1 Further readings 4 Further readings cont d Students interested in making a reference to a text book on the arguments covered in this lecture can refer for instance to J P Hayes Introduction to Digital Logic Design Addison Wesley Reading MA USA 1994 chapter 7 pp 490 555 M Morris Mano C R Kime Logic and Computer Design Fundamentals 2nd edition updated Prentice Hall Upple Saddle River NJ USA 2001 chapter 4 pp 201 224 or to 7 1 P Prinetto all rights reserved 5 7 1 Version 1 0 6 7 1 1 ECE 465 7 1 Logic level sequential design 1 Outline Global overview Global overview We shall present the overall set of steps first RT level formalization 7 1 7 User s Requirements 7 1 8 Manual synthesis Goal User s Requirements system system Logic level Synthesis RT RT logic logic device device behavior structure 7 1 physical behavior 9 10 User s Requirements RT level formalization system RT device physical Manual synthesis User s Requirements logic structure 7 1 Manual synthesis system RT level formalization RT level formalization RT Aims at finding a representation of the temporal evolution of the states of the system behavior structure 1 P Prinetto all rights reserved 0 A 0 physical 0 0 D 1 7 1 STG logic reset 11 7 1 Version 1 0 1 B 0 Aims at finding a representation of the temporal evolution of the states of the system device1 behavior 1 0 structure physical C 0 12 7 1 2 ECE 465 7 1



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