Logic level sequential blocksGoalPrerequisitesHomeworkFurther readingsSlide 6OutlineLogic level elementary sequential blocksLatch vs. Flip-flopSlide 10Slide 11Pro’s & Con’sLatchD latchSlide 15Slide 16Slide 17WaveformsHazard-free polarity hold latchSet-Reset latchSlide 21Slide 22Set-Reset latch (nand implementation)Slide 24Slide 25Slide 26Slide 27Slide 28Set-Reset latch (nor implementation)Slide 30Gated Set-Reset latchPossible implementationExcitation tableSlide 34Slide 35Flip-FlopTemporal constraintsPowerPoint PresentationSlide 39FF classification w.r.t. data inputsD behaviorSlide 42CaveatExample (D = data input)Example (D = control input)Set-Reset behaviorSlide 47JK behaviorSlide 49D FF implemented by a JK FFT behaviorSlide 52Slide 53T FF implemented by a JK FFT FF implemented by a D FFD FF implemented by a T FFD FF positive edge triggered implemented by latchesSlide 58D FF positive edge triggered implemented in TTL logic (‘74)The D FF as a library cellFlip flop D: I/O signalsFlip flop D: symbolFlip flop D: Asynchronous clearFlip flop D: Synchronous clearFlip flop D: Synchronous presetFlip flop D: Data loadFlip flop D: Data holdSlide 68Scannable Flip-flopsSlide 70Slide 71Flip-flop scannableImplementationsMux-scan approachClock-scan approachSlide 76Logic level Logic level sequential blockssequential blocksLogic level Logic level sequential blockssequential blocksPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected] [email protected] 5.22 5.2 Goal-This lecture presents the set of functional sequential blocks that are usually considered to be “elementary” or “basic” at the logic level.3 5.2 Prerequisites -Module 3 and 44 5.2 Homework -No particular homework is foreseen5 5.2 Further readings -Students interested in making a reference to a text book on the arguments covered in this lecture can refer, for instance, to:M. Morris Mano, C.R.Kime: “Logic and Computer Design Fundamentals,” 2nd edition updatedPrentice Hall, Upple Saddle River, NJ (USA), 2001, (chapter 4, pp. 182-201)6 5.2 Further readings or to:J. P. Hayes:“Introduction to Digital Logic Design,”Addison Wesley, Reading, MA (USA), 1994, (chapter 6, pp. 390-453)7 5.2 OutlineOutline-Latch-Flip-flop-Scannable Flip-flop8 5.2 behavior structure physicalsystemRTlogicdeviceLogic level elementary sequential blocksDevices capable of Devices capable of storing a single bit:storing a single bit:•latchlatch•flip-flopflip-flop9 5.2 CLKDLatch vs. Flip-flop10 5.2 CLKDQlatchLatch vs. Flip-flop11 5.2 CLKDQQflip-floplatchLatch vs. Flip-flop12 5.2 Pro’s & Con’sA latch is a Mealy machineA flip-flop is a Moore machineFlip-flops improve testability13 5.2 LatchLatchA latch is a single-bit storage device implemented as a Mealy machine.The most widely used is the so calledD latch.14 5.2 D latch1DQQNC1IEEE Symbol15 5.2 D latch1DQQNC1IEEE SymbolCharacteristicTable16 5.2 D latch1DQQNC1IEEE SymbolCharacteristicTableDescribes the logical properties of the latch by describing its operation in tabular form17 5.2 D latch1DQQNC1IEEE SymbolC D Q QN0 - Q-1QN-11 0 0 11 1 1 0 CharacteristicTablePrevious value of Q18 5.2 WaveformsCDQC D 1S 1R Q QN0 - 1 1 Q-1QN-11 0 1 0 0 11 1 0 1 1 019 5.2 DCQQNHazard-free polarity hold latchWithin the in-house developed LSSD design methodology, IBM uses the following implementation:20 5.2 Set-Reset latch-The Set-Reset latch can be considered the elementary building block for the implementation of all synchronous sequential circuits.-It has:2 inputs S and R 2 output Q and QN, such that QN = Q’.SRQQN21 5.2 Set-Reset latch-The Set-Reset latch can be considered the elementary building block for the implementation of all synchronous sequential circuits.-It has:2 inputs S and R 2 output Q and QN, such that QN = Q’.Of the 4 combinations of S and R:-One forces Q QN = 0 1 (reset)-One forces Q QN = 1 0 (set)-One lets Q QN unchanged-One is forbiddenSRQQN22 5.2 Set-Reset latch-The Set-Reset latch can be considered the elementary building block for the implementation of all synchronous sequential circuits.-It has:2 inputs S and R 2 output Q and QN, such that QN = Q’.Of the 4 combinations of S and R:-One forces Q QN = 0 1 (reset)-One forces Q QN = 1 0 (set)-One lets Q QN unchanged-One is forbiddenSRQQNThe correspondenceinput combination  performed operationis technology and implementation dependent23 5.2 Set-Reset latch (nand implementation)SRQQN24 5.2 Set-Reset latch (nand implementation)SRSRQQNQNQQ-125 5.2 00 01 11 10 0 1 1 0 01 1 1 1 0 S RQQ-1Karnaugh MapSet-Reset latch (nand implementation)26 5.2 00 01 11 10 0 1 1 0 01 1 1 1 0 S RQQ-1S R Q QN0 0 1 10 1 1 01 0 0 11 1 Q-1 QN-1CharacteristicTableKarnaugh MapSet-Reset latch (nand implementation)27 5.2 00 01 11 10 0 1 1 0 01 1 1 1 0 S RQ-1S R Q QN0 0 1 10 1 1 01 0 0 11 1 Q-1 QN-1CharacteristicTableKarnaugh MapSet-Reset latch (nand implementation)This combination is forbidden due to:-It forces both outputs to 1, thus preventing QN = Q’-a transition S R = 00  S R = 11forces the circuit to enter an unpredictable state, whose value depends from internal delays.28 5.2 00 01 11 10 0 1 1 0 01 1 1 1 0 S RQQ-1S R Q QN0 0 1 10 1 1 01 0 0 11 1 Q-1 QN-1Q-1 Q S R0  0 1 -0  1 0 11  0 1 01  1 - 1TransitionTableCharacteristicTableKarnaugh MapSet-Reset latch (nand implementation)29 5.2 SRQQNSet-Reset latch (nor implementation)30 5.2 00 01 11 10 0 0 1 0 01 1 1 0 0 S RQQ-1S R Q QN0 0 Q-1 QN-10 1 1 01 0 0 11 1 0 0Q-1 Q S R0  0 - 00  1 0 11  0 1 01  1 0 -TransitionTableCharacteristicTableKarnaugh MapSet-Reset latch (nor implementation)31 5.2 Gated Set-Reset latchIt’s a variation of the Set-Reset latch, in which data are allowed to enter the latch when a given control signal C is asserted, only.1S1RQQNC1Symbol IEEE32 5.2 SiRiQQN1S1RC1Possible implementation33 5.2 C1 1S 1R Si RiQ QN0 - - 1 1 Q-1 QN-11 0 0 1 1 Q-1 QN-11 0 1 1 0 0 11 1 0 0 1 1 0 1 1 1 0 0Excitation table34 5.2 OutlineOutline-Latch Flip-flop-Scannable Flip-flop35 5.2 behavior structure physicalsystemRTlogicdeviceDevices capable of Devices capable of storing a single bit:storing a single bit:•latchlatch flip-flopflip-flopLogic level elementary