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UIC ECE 465 - An Introduction to Digital Systems Simulation

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© P.Prinetto - all rights reserved Version 1.0 10.1.110.1 – An introduction to Digital Systems Simulation ECE 465An Introduction to Digital Systems SimulationPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected]@uic.eduwww.testgroup.polito.itLecture 10.1210.1 Goal• This lecture presents a brief introduction to digital system simulation• The use of a simulation tool for Validation &Verification is targeted as well.310.1 Prerequisites • Module 4 410.1 Homework • No particular homework is foreseen510.1 Further readings • Students interested in a deeper knowledge of simulation algorithms can refer, for instance, to:− M. Abramovici, M.A. Breuer, A.D. Friedman: “Digital System Testing and Testable Design (revised printing),” IEEE Press, Piscataway, NJ (USA), 1990 (chapter 3, pp. 39-91)610.1 Outline• Introduction• Simulation tool architecture• Using a simulation tool for Validation &Verification.© P.Prinetto - all rights reserved Version 1.0 10.1.210.1 – An introduction to Digital Systems Simulation ECE 465710.1 Simulating a system consists in analyzing the behavior of a model of the system itself. Simulation810.1 Simulating a system consists in analyzing the behavior of a model of the system itself. SimulationUsually extracted from the system description910.1 Simulating a system consists in analyzing the behavior of a model of the system itself. SimulationUsually generatedfrom the system descriptionAccording to its accuracy, different information can be extracted from the simulation experiment1010.1 StatusSimulation is the industrial usual approach for: • project debugging• verification• validation• design rule checking• performances analysis • timing analysis• …1110.1 Outline• Introduction⇒Simulation tool architecture• Using a simulation tool for Validation &Verification1210.1 Circuit descriptionInputWaveforms GeneratorSimulationCommandsOutput Waveforms AnalyzerSimulation EngineLibraries© P.Prinetto - all rights reserved Version 1.0 10.1.310.1 – An introduction to Digital Systems Simulation ECE 4651310.1 Circuit descriptionInputWaveforms GeneratorSimulationCommandsOutput Waveforms AnalyzerSimulation EngineLibrariesComputes the output waveformsof the system, starting from the circuit descriptionand the input waveforms1410.1 Circuit descriptionInputWaveforms GeneratorSimulationCommandsOutput Waveforms AnalyzerSimulation EngineLibrariespattern i 00 01 10 11pattern i < file1.patwfm a @0=1 @10=0 10=1 15=0 @50=1wfm a @0=0 @100=1 (200=0 200=1)*2wfm a @0=00\H (1000 = inc by 1\D)*41510.1 Circuit descriptionSimulationCommandsOutput Waveforms AnalyzerSimulation EngineLibrariesWaveform interpreterInput waveforms1610.1 Circuit descriptionSimulationCommandsOutput Waveforms AnalyzerSimulation EngineLibrariesWaveform interpreterInput waveforms|Simulate the circuitRUNsim 10nscycle 10step next1710.1 Circuit descriptionOutput Waveforms AnalyzerSimulation EngineLibrariesWaveform interpreterInput waveformsCommand interpreterSimulation commands1810.1 Output Waveforms AnalyzerSimulation EngineLibrariesWaveform interpreterInput waveformsCommand interpreterSimulation commandsDesignData BaseNetwork descriptionNetwork linkerHardware modeller© P.Prinetto - all rights reserved Version 1.0 10.1.410.1 – An introduction to Digital Systems Simulation ECE 4651910.1 Output Waveforms AnalyzerSimulation EngineLibrariesWaveform interpreterInput waveformsCommand interpreterSimulation commandsDesignData BaseNetwork descriptionNetwork linkerHardware modellerABCDE2010.1 Simulation EngineLibrariesWaveform interpreterInput waveformsCommand interpreterSimulation commandsOutput waveformsWaveform analyzerDesignData BaseNetwork descriptionNetwork linkerHardware modeller2110.1 Simulation EngineLibrariesWaveform interpreterInput waveformsCommand interpreterSimulation commandsOutput waveformsWaveform analyzerDesignData BaseNetwork descriptionNetwork linkerHardware modellerLibraries2210.1 Outline• Introduction• Simulation tool architecture⇒Using a simulation tool for Validation & Verification2310.1 Be careful:Exhaustive Simulation is mostly unfeasible2410.1 Just an example...Exhaustively simulating a 32 bit adder requires applying265input valuesAssuming simulating a single value require 1 ns, the whole simulation process would requires 1,100+ years !!!!© P.Prinetto - all rights reserved Version 1.0 10.1.510.1 – An introduction to Digital Systems Simulation ECE 4652510.1 A further example...CPU Intel 8080:• about 120 latches• 256 machine instructions• 8-bit and 16-bit operands:3.15 ⋅ 1045 instructions2610.1 A further example...CPU Intel 8080:• about 120 latches• 256 machine instructions• 8-bit and 16-bit operands:3.15 ⋅ 1045 instructions1032 yearsThe life of our Universe is estimated 2 · 1010years !2710.1 A basic approach to V&V • Identify the set of peculiar aspects, or properties, of the design that need to be checked2810.1 A basic approach to V&V • Identify the set of peculiar aspects, or properties, of the design that need to be checked• Organize your V&V operations as a set of independent sessions, each aiming at checking the correctness of some of the above selected peculiar aspects or properties.2910.1 A simulation session • For each target aspect or property:− State how to check it− Select the minimum set of input values needed − For each selected value, state the expected output− Identify the most efficient way for:⋅ applying the input values⋅ analyzing the circuit behavior.3010.1 A simulation session (cont’d)• Hints:− Simulate the basic behaviors of the system, first− Then, focus on potential critical situations:⋅ Identify border line conditions between alternative behaviors (e.g., change the status of the circuit)⋅ Force the circuit to reach border line conditions© P.Prinetto - all rights reserved Version 1.0 10.1.610.1 – An introduction to Digital Systems Simulation ECE 4653110.1 Identify the most efficient way to perform simulation experimentsA simulation experiment can be performed in either way:• resorting to a VHDL Test Bench (highly recommended)• controlling the experiment manually, in a highly interactive manner (for expert designers or for fine tuning and debugging).3210.1 The basic principleVHDL Description of the target system3310.1 The basic principleVHDL Description of the target systemTest Bench3410.1 The


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