© P.Prinetto - all rights reserved Version 3.0 9.0.1Module 9 : VHDL-based SynthesisECE 465 - Digital Systems DesignModule 9 :VHDL-based SynthesisPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected]@uic.eduwww.testgroup.polito.itModule 929.0 Goal• This module presents the basic concept of VHDL-based Synthesis• The first lecture presents several description styles• The second lecture presents many examples of VHDL descriptions at various abstraction levels and description domains• VHDL files related to the solution of exercises proposed in Modules 6 and 7 are available to be downloaded.39.0 Prerequisites • Students have to be familiar with the basic concepts of VHDL language (see Module 8).49.0 Structure• This module includes the following 6 lectures:− 9.1 VHDL description styles− 9.2 Some examples59.0 Examples & Exercises• The complete solutions of some Exercises and Examples proposed within the Lectures are available 69.0 VHDL files• The VHDL files (.vhd) related to several exercises and examples solved within the lectures are available.• They are zipped in 2 files, related to Exercises and to Examples proposed within the Lectures, respectively.© P.Prinetto - all rights reserved Version 3.0 9.0.2Module 9 : VHDL-based SynthesisECE 465 - Digital Systems
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