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Combinational design: the basic approachGoalPrerequisitesHomeworkFurther readingsOutlineLogic level designStep #1: Specification preparationSlide 9Step #2: Specification validationStep #3: SynthesisSlide 12Manual synthesis approachesPurely manual approachPurely manual approach (cont’d)Partially automated approachSlide 17Partitioning-bases approachSlide 19Partitioning-bases approach (cont’d)Slide 21Manual synthesis stepsStep #3.1: Logic level refinementsSlide 24Slide 25Slide 26Step #3.1.1: 1st refinementsSlide 28Slide 29Step #3.1.2: Logic minimizationSlide 31Slide 32NoteStep #3.2: Library bindingSlide 35Slide 36Slide 37ExampleSlide 39Slide 40Slide 41Slide 42Multiple outputsSlide 44Slide 45Slide 46Step #3.3: Technology mappingSlide 48Slide 49Slide 50Library partsSolutionPowerPoint PresentationCombinational Combinational design:design:the basic approachthe basic approachCombinational Combinational design:design:the basic approachthe basic approachPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected] [email protected] 6.12 6.1 Goal-This lecture presents the basic approach to manual synthesis of Combinational networks.3 6.1 Prerequisites -Modules 4 and 5, and Lecture 2.14 6.1 Homework -No particular homework is foreseen5 6.1 Further readings -No particular suggestion6 6.1 Outline-Manual synthesis approaches-Manual synthesis steps7 6.1 Logic level design behavior structure physicalsystemRTlogicUser'sRequirementsImplImpl8 6.1 behavior structure physicalStep #1: Specification preparationsystemRTlogicSpecsSpecsUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?9 6.1 behavior structure physicalStep #1: Specification preparationsystemRTlogicSystem level, System level, behavioral behavioral descriptiondescriptionSpecsSpecsUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?10 6.1 behavior structure physicalStep #2: Specification validationsystemRTlogic=?=?SpecsSpecsUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?11 6.1 behavior structure physicalStep #3: SynthesissystemRTlogicImplSpecsSpecsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?12 6.1 behavior structure physicalStep #3: SynthesissystemRTlogicImplLogic level, Logic level, physical domain physical domain netlist descriptionnetlist descriptionSpecsSpecsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?13 6.1 Manual synthesis approachesSeveral approaches are possible, not necessarily strictly each other orthogonal.They could be classified as follows:-Purely manual-Partially automated-Partitioning based.14 6.1 Purely manual approach-Karnaugh map based-When performing a manual synthesis it is:rather easy to minimize the maximum delay (by designing 2-logic-level circuits, only)extremely hard to minimize the area, trading off with the maximum delay.15 6.1 Purely manual approach (cont’d)-Applicable when dealing with very few PIs, only (PIs  6)-It will be presented in the sequel of this lecture.16 6.1 Partially automated approach-Some of the sub-steps can be accomplished resorting to tools freely downloadable from the web-Applicable when the behavior of each PO has been described by a Boolean Function expressed as a set of cubes17 6.1 Partially automated approach-Some of the sub-steps can be accomplished resorting to tools freely downloadable from the web-Applicable when the behavior of each PO has been described by a Boolean Function expressed as a set of cubes-No significant limitation w.r.t. the # of PIs.-It will be presented in lecture 6.4.18 6.1 Partitioning-bases approach-The system is first partitioned in functional blocks-Each functional block is then implemented resorting to one of the above mentioned approaches-The system is eventually designed simply assembling the functional blocks19 6.1 Partitioning-bases approach-The system is first partitioned in functional blocks-Each functional block is then implemented resorting to one of the above mentioned approaches-The system is eventually designed simply assembling the functional blocks-No significant limitation w.r.t. the # of PIs-It will be presented in lecture 6.520 6.1 Partitioning-bases approach (cont’d)-Historically this method was thoroughly applied in the 70’s and 80’s when digital systems were mainly implemented by PCBs and the chips available were mostly the RT level basic blocks presented in lecture 5.2 and 5.3.21 6.1 Outline-Manual synthesis approaches Manual synthesis steps22 6.1 Manual synthesis steps Manual synthesis is usually performed in several sub-steps.23 6.1 behavior structure physicalStep #3.1: Logic level refinementssystemRTlogicSpecsSpecs24 6.1 behavior structure physicalStep #3.1: Logic level refinementssystemRTlogicSpecsSpecs25 6.1 behavior structure physicalStep #3.1: Logic level refinementssystemRTlogicSpecsSpecsBoolean Boolean functionfunction of each PO of each POU = A’B’ + A DU = A’B’ + A D26 6.1 It’s usually performed in 2 sub-sub-phases:Step #3.1: Logic level refinements27 6.1 Step #3.1.1: 1st refinements behavior structure physicalsystemRTlogicSpecsSpecs28 6.1 Step #3.1.1: 1st refinements behavior structure physicalsystemRTlogicSpecsSpecsNon-minimal Non-minimal Boolean Boolean functionfunction of each PO of each PO29 6.1 Step #3.1.1: 1st refinements behavior structure physicalsystemRTlogicSpecsSpecsNon-minimal Non-minimal Boolean Boolean functionfunction of each PO of each POUsually accomplished by drawing the Karnaugh map of each POABABCDCD000001011111101000001100 - - 0 001011100 - - 1 111111100 - - - -1010110 0 - - - -30 6.1 behavior structure physicalStep #3.1.2: Logic minimizationsystemRTlogic31 6.1 behavior structure physicalStep #3.1.2: Logic minimizationsystemRTlogicMinimized Minimized Boolean functionBoolean function of each PO of each PO32 6.1 behavior structure physicalStep #3.1.2: Logic minimizationsystemRTlogicMinimized Minimized Boolean functionBoolean function of each PO of each POU = A’B’ + A DU = A’B’ + A D33 6.1


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