Typical design processesGoalHomeworkPrerequisitesFurther readingsOutlineEDA-tool centered design processesStep #0: EDA tool environment preparationStep #1: Specification preparationSlide 10Slide 11Step #2: Specification validationSlide 13Slide 14Step #3: SynthesisSlide 16Slide 17Intermediate stepsStep #3.1: Behavioral SynthesisSlide 20Step #3.1: Behavioral SynthesisStep #3.2: RT level synthesisSlide 23Slide 24Step #4: Specs vs Impl verificationSlide 26Slide 27Slide 28Step #5: Implementation validationSlide 30Slide 31Slide 32Slide 33Manual design processesSlide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Synthesis methodologiesStep #4: Specs vs. Impl verificationSlide 46Slide 47Slide 48Slide 49Slide 50PowerPoint PresentationTypical design Typical design processesprocessesTypical design Typical design processesprocessesPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected] [email protected] 2.52 2.5 Goal-This lecture presents 2 typical design processes, the former being “EDA-tool” centered, the latter mostly manual, i.e., performed without the aid of any tool.3 2.5 Homework -No particular homework is foreseen4 2.5 Prerequisites -Lecture # 2.45 2.5 Further readings -No particular suggestion6 2.5 OutlineOutline-EDA-tool centered design process-Manual design process7 2.5 EDA-tool centered design processesEDA-tool centered design processes-In the following, we present a “typical” up-to-date EDA-tool centered design process.8 2.5 Step #0: EDA tool environmentpreparationGoal:-Set up the project design environment on the target EDA systembehavior structure physicalStep #1: Specification preparationsystemRTlogicUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsbehavior structure physicalStep #1: Specification preparationsystemRTlogicSpecsSpecsUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirements11 2.5 Goal:-Get a description of the behavior of the target systemTools:-Brain, experience-Editor-Compiler of the chosen HDLStep #1: Specification preparationbehavior structure physicalStep #2: Specification validationsystemRTlogicSpecsSpecsUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsbehavior structure physicalStep #2: Specification validationsystemRTlogic=?=?SpecsSpecsUser'sRequirementsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirements14 2.5 Goal:-Check that the behavioral description fulfills user’s requirementsTools:-HDL simulatorStep #2: Specification validationbehavior structure physicalStep #3: SynthesissystemRTlogicSpecsSpecsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsbehavior structure physicalStep #3: SynthesissystemRTlogicImplSpecsSpecsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirements17 2.5 Goal:-Get a netlist, in the selected technology library, which is a proper implementation of the behavioral descriptionTools:-Automated Synthesis toolsStep #3: Synthesis18 2.5 Intermediate steps-Synthesis is today mostly performed in 2 intermediate stepsbehavior structure physicalStep #3.1: Behavioral SynthesissystemRTlogicSpecsSpecsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsbehavior structure physicalStep #3.1: Behavioral SynthesissystemRTlogicSpecsSpecsDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsRT levelRT level21 2.5 Goal:-Get a RT level behavioral descriptionTools:-Automated Behavioral Synthesis tools (if available)-Manual writing of the RT level codeStep #3.1: Behavioral Synthesisbehavior structure physicalStep #3.2: RT level synthesissystemRTlogicDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsRT levelRT levelbehavior structure physicalStep #3.2: RT level synthesissystemRTlogicImplDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsDesignDesignrulesrulesDesignDesignrulesrulesSpecificationSpecification=?=?=?=?=?=?ImplementationImplementation=?=?RequirementsRequirementsRT levelRT level24 2.5 Goal:-Get a netlist, in the selected technology library, which is a proper implementation of the behavioral descriptionTools:-Automated RT level synthesis toolsStep #3.2: RT level synthesisbehavior structure physicalStep #4: Specs vs Impl