© P.Prinetto - all rights reserved Version 1.0 7.3.17.3 – Some examplesECE 465Some examplesPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected]@uic.eduwww.testgroup.polito.itLecture 7.327.3 Goal• This lecture guides the students through the solution of some simple examples of manual synthesis of sequential networks.37.3 Prerequisites • Lectures 7.1 and 7.247.3 Homework • Students are recommended to try to solve the exercise by themselves, before looking at the proposed solutions.57.3 Further readings • No particular suggestion67.3 Outline• Example #7.3.1: rising edge detector• Example #7.3.2: palindrome string detector• Example #7.3.3: BCD big endian• Example #7.3.4: BCD little endian• Example #7.3.5: parity checker• Example #7.3.6: Ford Thunderbird light controller• Example #7.3.7: code checker• Example #7.3.8: sequence checker© P.Prinetto - all rights reserved Version 1.0 7.3.27.3 – Some examplesECE 46577.3 Example #7.3.1: rising edge detectorA circuit is to be designed, having:• An input X• A clock signal CLK, which acts as a proper sampling signal of X, i.e., the frequency of CLK is such that it never happens that two transitions of X occur within a same CLK cycle• An output U, asserted for a clock cycle whenever a rising edge on the input X is detected.87.3 CLKXWaveforms97.3 CLKXZWaveforms107.3 STGresetH0,0117.3 STGreset1H0,0127.3 STGL,0reset10H0,0© P.Prinetto - all rights reserved Version 1.0 7.3.37.3 – Some examplesECE 465137.3 STGL,0reset100H0,0147.3 STGL,0H1,1reset1010H0,0157.3 STGL,0H1,1reset1010H0,00167.3 STGL,0H1,1reset1010H0,001177.3 State encodingstate encodingH0 00L11H1 10STTL,0H1,1reset1010H0,001state encodingH0 00L11H1 10© P.Prinetto - all rights reserved Version 1.0 7.3.47.3 – Some examplesECE 465STTL,0H1,1reset1010H0,001state encodingH0 00L11H1 1001H0 ≡ 00 11 00 001 - - 0L ≡ 11 11 10 0H1 ≡ 10 11 00 1y[1:0]xY[1:0] Z207.3 STT01H0 ≡ 00 11 00 001 - - 0L ≡ 11 11 10 0H1 ≡ 10 11 00 1y[1:0]xY[1:0] ZY[1] = x’ + y[0]Y[0] = x’Z = y[1]y[0]’217.3 DDxZD[1] = x’ + y[0]D[0] = x’Z = y[1]y[0]’SolutionD[0]y[1]y[0]D[1]227.3 Outline• Example #7.3.1: rising edge detector⇒Example #7.3.2: palindrome string detector• Example #7.3.3: BCD big endian• Example #7.3.4: BCD little endian• Example #7.3.5: parity checker• Example #7.3.6: Ford Thunderbird light controller• Example #7.3.7: code checker• Example #7.3.8: sequence checker237.3 Example #7.3.2: palindrome string detectorOn a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle.A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.247.3 Example #7.3.2: palindrome string detectorOn a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle.A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.Examples:ANNA – 3993 – 0110© P.Prinetto - all rights reserved Version 1.0 7.3.57.3 – Some examplesECE 465257.3 -01reset267.3 -01010101reset277.3 -010111001001010101011001reset287.3 -01011100100111110001000101010010011110011010reset297.3 -0101110010011111000100011011110000100101010100100111100110100 1101001U=0U=1reset307.3 -0101110010011111000100011011110000100101010100100111100110100 1101001U=0U=1reset© P.Prinetto - all rights reserved Version 1.0 7.3.67.3 – Some examplesECE 465317.3 Outline• Example #7.3.1: rising edge detector• Example #7.3.2: palindrome string detector⇒Example #7.3.3: BCD big endian• Example #7.3.4: BCD little endian• Example #7.3.5: parity checker• Example #7.3.6: Ford Thunderbird light controller• Example #7.3.7: code checker• Example #7.3.8: sequence checker327.3 Example #7.3.3: BCD big endianOn a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 4 bits: each group corresponding to a BCD digit, transmitted MSB first (big endian)A circuit to be connected to the serial line is to be designed. It has an output U which is asserted, for 1 clock cycle, in correspondence of the 4thbit of each group, if the group itself is a correct BCD digit. BCD337.3 SolutionWhen dealing with circuits that must consider groups of bits, it may be convenient to start from a set of states, one for each possible combination of the PO values.BCD347.3 SolutionA,0 E,1reset0110BCD357.3 SolutionA,0 E,1B,0reset0110-BCD367.3 SolutionA,0 E,1B,0reset0110C,0--BCD© P.Prinetto - all rights reserved Version 1.0 7.3.77.3 – Some examplesECE 465377.3 SolutionA,0 E,1B,0reset0110C,0D,0---BCD387.3 SolutionA,0 E,1B,0F,0reset0110C,0D,0---BCD397.3 SolutionA,0 E,1B,0F,0reset0110C,0D,0--H,01-BCD407.3 SolutionA,0 E,1B,0F,0reset0110C,0D,0I,0--H,0-1--BCD417.3 SolutionA,0 E,1B,0F,0reset01010C,0 G,00D,0I,0--H,0-11--BCD427.3 Outline• Example #7.3.1: rising edge detector• Example #7.3.2: palindrome string detector• Example #7.3.3: BCD big endian⇒Example #7.3.4: BCD little endian• Example #7.3.5: parity checker• Example #7.3.6: Ford Thunderbird light controller• Example #7.3.7: code checker• Example #7.3.8: sequence checker© P.Prinetto - all rights reserved Version 1.0 7.3.87.3 – Some examplesECE 465437.3 Example #7.3.4: BCD little endianSimilar to the previous exercise, with the only difference that BCD digits are transmitted LSB first.BCD447.3 Valid Sequences0000 0 Y0001 8 Y0010 4 Y0011 12 N0100 2 Y0101 10 N0110 6 Y0111 14 N1000 1 Y1001 9 Y1010 5 Y1011 13 N1100 3 Y1101 11 N1110 7 Y1111 15 NBCD457.3 A,0 E,1B,0reset−C,0F,0D,0G,0−1−−010E01EABCD467.3 Outline• Example #7.3.1: rising edge detector• Example #7.3.2: palindrome string detector• Example #7.3.3: BCD big endian• Example #7.3.4: BCD little endian⇒Example #7.3.5: parity checker• Example #7.3.6: Ford Thunderbird light controller• Example #7.3.7: code checker• Example #7.3.8: sequence checker477.3 Example #7.3.5: parity checkerOn a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit strings of 4 bitsA circuit to be