© P.Prinetto - all rights reserved Version 1.0 5.3.15.3 – RT level sequential blocksECE 465RT level sequential blocksPaolo PRINETTOPolitecnico di Torino (Italy)University of Illinois at Chicago, IL (USA)[email protected]@uic.eduwww.testgroup.polito.itLecture 5.325.3 Goal• This lecture presents the set of functional sequential blocks that are usually considered to be “elementary” or “basic” at the RT level.35.3 Prerequisites• Module 4 and lecture 7.145.3 Homework• No particular homework is foreseen55.3 Further readings• Students interested in making a reference to a text book on the arguments covered in this lecture can refer, for instance, to:− M. Morris Mano, C.R.Kime: “Logic and Computer Design Fundamentals,” 2nd edition updatedPrentice Hall, Upple Saddle River, NJ (USA), 2001, (chapter 3, pp. 111-148 )65.3 OutlineRegisterShift registerRAMCounter© P.Prinetto - all rights reserved Version 1.0 5.3.25.3 – RT level sequential blocksECE 46575.3 OutlineRegisterShift registerRAMCounter85.3 RegisterAn n-bit register is a sequential functional block able to perform the following operations:• asynchronous clear• synchronous clear • n-bit data parallel load• stored data hold95.3 Register: I/O signalsInput Data signals : D_IN (n-1 downto 0)Output Data signals : D_OUT (n-1 downto 0)Clock signal : CLKReset signal : ASYNC_CLRInput Control signals : CLK_EN,SYNC_CLROutput Control signals : none105.3 Register: symbolD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLK115.3 Register: Asynchronous clearD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLK125.3 Register: Asynchronous clearD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLK1----000..00ASYNC_CLR = 1⇓D_OUT = 000..00© P.Prinetto - all rights reserved Version 1.0 5.3.35.3 – RT level sequential blocksECE 465135.3 Register: Data holdD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLK0--0-ASYNC_CLR = 0CLK_EN = 0⇓D_OUTt+1= D_OUTt145.3 Register: Synchronous clearD_IN D_OUTASYNC_CLRSYNC_CLRCLK_EN0-11↑000..00ASYNC_CLR = 0CLK_EN = 1SYNC_CLR = 1CLOCK ↑⇓D_OUT = 000..00CLK155.3 Register: Parallel loadD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLK001↑ASYNC_CLR = 0CLK_EN = 1SYNC_CLR = 0CLOCK ↑⇓D_OUT = D_INvalue value165.3 OutlineRegisterShift registerRAMCounter175.3 CounterTwo kinds of counters will be considered:• Up-down modulo m counters• 1-to-m up counters185.3 Up-down modulo m countersAn up-down modulo m counter is a sequential functional block able to perform the following operations:• asynchronous clear• synchronous clear• n-bit data parallel load• holding the stored data• incrementing, modulo m, the stored data• decrementing, modulo m, the stored data© P.Prinetto - all rights reserved Version 1.0 5.3.45.3 – RT level sequential blocksECE 465195.3 The concept of moduloEach counter is characterized by its modulo, i.e., the maximum number m of different output configurations it can get.It must obviously be:m ≤ 2 # FFsA modulo m counter (often referred to as |m|) gets all the values between 0 and m -1.205.3 I/O signalsInput Data signals : D_IN (n-1 downto 0)Output Data signals : D_OUT (n-1 downto 0)Clock signal : CLKReset signal : ASYNC_CLRInput Control signals : CLK_EN,SYNC_CLR,LD/~CNT,UP/~DN Output Control signals : TC215.3 I/O signalsInput Data signals : D_IN (n-1 downto 0)Output Data signals : D_OUT (n-1 downto 0)Clock signal : CLKReset signal : ASYNC_CLRInput Control signals : CLK_EN,SYNC_CLR,LD/~CNT,UP/~DN Output Control signals : TCOperation selection: it enablesparallel loadingwhen asserted,countingotherwise Counting direction225.3 I/O signalsInput Data signals : D_IN (n-1 downto 0)Output Data signals : D_OUT (n-1 downto 0)Clock signal : CLKReset signal : ASYNC_CLRInput Control signals : CLK_EN,SYNC_CLR,LD/~CNT,UP/~DN Output Control signals : TCTerminal Count: asserted when the counter is enabled and a counting limit is reached:m-1 when counting up0 when counting down235.3 SymbolD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLKLD/~CNTUP/~DNTC|m|245.3 Counter: Parallel loadvalue001↑D_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENLD/~CNTUP/~DNTC1-CLK|m|© P.Prinetto - all rights reserved Version 1.0 5.3.55.3 – RT level sequential blocksECE 465255.3 Counter: Parallel loadvalue001↑D_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENLD/~CNTUP/~DNTC1-0ASYNC_CLR = 0CLK_EN = 1SYNC_CLR = 0CLOCK ↑⇓D_OUT = D_INTC = 0valueCLK|m|265.3 Counter: Increment operation001↑D_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENLD/~CNTUP/~DNTC01-CLK|m|275.3 Counter: Increment operation001↑D_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENLD/~CNTUP/~DNTC01ASYNC_CLR = 0CLK_EN = 1SYNC_CLR = 0LD/~CNT = 0UP/~DN = 1CLOCK ↑⇓D_OUTt+1=(D_OUTt+ 1) mod mUpdate TC-CLK|m|285.3 Counter: Decrement operation001↑D_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENLD/~CNTUP/~DNTC00-CLK|m|295.3 Counter: Decrement operation001↑D_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENLD/~CNTUP/~DNTC00ASYNC_CLR = 0CLK_EN = 1SYNC_CLR = 0LD/~CNT = 0UP/~DN = 0CLOCK ↑⇓D_OUTt+1=(D_OUTt- 1) mod mUpdate TC-CLK|m|305.3 1-to-m up countersA 1-to-m up counter is a sequential functional block able to perform the following operations:• asynchronous clear• synchronous clear• n-bit data parallel load• holding the stored data• incrementing the stored data from 1 to m© P.Prinetto - all rights reserved Version 1.0 5.3.65.3 – RT level sequential blocksECE 465315.3 Counting behaviorThe major difference w.r.t. the up-down counter is that, in this case, counting is performed from 1 to m: when the value m is reached, the output TC is asserted and the next value is 1.325.3 I/O signalsInput Data signals : D_IN (n-1 downto 0)Output Data signals : D_OUT (n-1 downto 0)Clock signal : CLKReset signal : ASYNC_CLRInput Control signals : CLK_EN,SYNC_CLR,LD/~CNT,Output Control signals : TC335.3 SymbolD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLKLD/~CNTTC1 to m345.3 OutlineRegisterShift registerRAMCounter355.3 Shift registerA shift register is a sequential functional block able to perform the following operations:• parallel load of an n-bit data • stored data retention • asynchronous clear• synchronous clear• stored data right shift• stored data left shift.365.3 Shift register : symbolD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLKLEFT_INLOAD/~SHIFTRIGHT/~LEFTRIGHT_IN© P.Prinetto - all rights reserved Version 1.0 5.3.75.3 – RT level sequential blocksECE 465375.3 Shift register : symbolD_IN D_OUTASYNC_CLRSYNC_CLRCLK_ENCLKLEFT_INLOAD/~SHIFTRIGHT/~LEFTRIGHT_INShifting directionOperation selection: it enablesparallel loadingwhen asserted,shiftingotherwise385.3 Shift