1ECE 465Introduction to CPLDs and FPGAsShantanu DuttECE Dept.University of Illinois at ChicagoAcknowledgement: Extracted from lecture notes of Dr. Mohamed M.Elkhatib, German University of Cairo and Prof. Russell Tessier, Univ. of Massachusetts. Some modfications and additions done by Prof. Dutt.CPLD Families2CPLD Block DiagramFunction block (~ PLA w/ 1 o/pthat can be FF’ed)Programmable switch for interconnecting various FBsFFFFFFFFFF11000I/PsO/PsCrossbar SwitchAn individual switchIn a crossbar is adiamond switchCPLD Function BlockPLA-like AND arrayLiteral inputs (e.g., a, b, c)Extra function (e.g., g,h) i/ps for OR termExample functionf= ab+bc’+g+hD-FF2:1 Mux3Field Programmable Gate Arrays (FPGAs)FPGA Types(Anti-fuse technology)4FPGA FamiliesPSM: Programmable Switch Matrix (for making connections between interconnects of different channels). The structure shown only allows i-to-i connectionsCLB: Configuration Logic Block (programmable logic cell)Horizontalrouting(interconnect)channelVerticalroutingchannelsSRAM-type FPGA Interconnect Architecture Diamondswitch5SRAM-type FPGA InterconnectArchitecture (contd) PSMCell ConnectionMatrix (CCM)Configuration Logic Block (CLB)• 5-i/p function implemented using G, F and H LUTs (Look Up Tables) using Shannon’sExpansion: p(a,b,c,d,e) = a p(1, b, c, d, e) + a’ p(0, b, c, d, e) = a q(b,c,d,e) + a’r(b,c,d,e).q( ) impl. using LUT G, r impl. using LUT F and p=ag + a’h impl. using LUT H• The LUT o/ps can go through a FF (for seq. ckt design) or bypass it for a combinational o/p• This is called technology mapping: mapping the logic to CLB logic components6Technology MappingProgramming a CLB (contd)7Components of Modern FPGAs8Digital System: Implementation Spectrum–ASIC gives high performance at cost of inflexibility.–Processor is very flexible but not tuned to the application.–Reconfigurable hardware is a nice compromise.Microprocessor ReconfigurableHardwareASICSoftwareFirmwareHardwareSimplified FPGA Logic ElementLook-Up Table (LUT)StateOutInputsClockEnable9High-level Compilers & FPGAs–Difficult to estimate hardware resources.–Some parts of program more appropriate for processor (hardware/software codesign).–Compiler must parallelizecomputation across many resources. –Engineers like to write in C/VHDL/Verilograther than pushing little blocks around.for (i = 0; i<n, i++){c[i] = a[i] + b[i]}Some success storiesTranslating a Design to an FPGA–CAD to translate circuit from text description to physical implementation well understood.–Most current FPGA designers use register-transfer level specification (allocation and scheduling)–Same basic steps as ASIC design.RTL..C = A+B.CircuitAB+CArray10Circuit Compilation & Implementation: Basic Steps1. Technology Mapping2. Placement3. RoutingLUTLUT?Assign a logical LUT to a physical location.Select wire segmentsand switches forInterconnection.4. Convert all implementation “details” to FPGA programming info (configuration bits): LUT RAM bits, CCM & PSM FF/SRAM bits, etc.• Can store config bits on disk or ROM and load into FPGA as needed• Can thus use the FPGA to implement multiple digital systems (at different times or sometimes simultaneously in different FPGA partitions)Technology Mapping: A Simple ExampleFAABCoCiSMade of Full AddersA+B = DLogic synthesis tool reduces circuit toSOP form Co= ABCi+ ABCi+ ABCi+ ABCiS = ABCi+ ABCi+ ABCi+ ABCiLUTCoCiBALUTSCiBA11Processor + FPGA1. FPGA serves as coprocessor for data intensive applications – possible project.Three possibilitiesBackplane bus(e.g. PCI)ProcchipdaughtercardFPGAchipFPGAProc2. FPGA serves as embedded digital systemfor lower latency processing.“Reconfigurable Functional