MOS: Metal Oxide SemiconductornMOS and pMOSCMOS Inverter Cross-SectionCMOS Cadence LayoutMOS Transistor SwitchesSignal StrengthsCMOS InverterNAND and NOR CMOS GatesPass TransistorTransmission GatesTransmission Gate Application: Select MuxD LatchD Flip-FlopD Flip-Flop OperationMore CMOS GatesAnd More CMOS GatesAnd More CMOS Gates1Principles of VLSI Design CMPE 413CMOS BasicsMOS: Metal Oxide SemiconductorTransistors are built on a Silicon (semiconductor) substrate.Pure silicon has no free carriers and conducts poorly.Dopants are added to increase conductivity: extra electrons (n-type) or extra holes (p-type)MOS structure created by superimposing several layers of conducting, insulating and tran-sistor-forming materials.Metal gate has been replaced by polysilicon or poly in modern technologies.There are two types of MOS transistors:nMOS : Negatively doped silicon, rich in electrons.pMOS : Positively doped silicon, rich in holes.CMOS: Both type of transistors are used to construct any gate.2Principles of VLSI Design CMPE 413CMOS BasicsnMOS and pMOSFour terminal devices: Source, Gate, Drain, body (substrate, bulk).n+pGateSource Drainbulk SiSiO2Polysiliconn+SourceGateDrainn+n+p substrateThinOxidenMOSLWpMOSSiO2nGateSource Drainbulk SiPolysiliconp+ p+3Principles of VLSI Design CMPE 413CMOS BasicsCMOS Inverter Cross-Sectionn+n+p+glass(insulator)metal2metal1m1-m2 contact (via)p-substrate contact (cc)VDDn-diffusion contact (cc)polysilicon gate (poly )n-transistorp-transistorGNDn-substrate contact (cc)p-diffusion contact (cc)(source)(source)(Out)layer #1layer #2layer #3n+p+p+n-well (nwell)(drains)Cadence Layer's for AMI 0.6mm technologyp substrate (black background)(nactive)(pactive)4Principles of VLSI Design CMPE 413CMOS BasicsCMOS Cadence LayoutCadence Layout for the inverter on previous slide5Principles of VLSI Design CMPE 413CMOS BasicsMOS Transistor SwitchesWe can treat MOS transistors as simple on-off switches with a source (S), gate (G) (con-trols the state of the switch) and drain (D).1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V today, .....)0 represent low voltage - GND or VSS. (0V for digital circuits)gsdg = 0sdg = 1sdgsdsdsdnMOSpMOSOFFONONOFF6Principles of VLSI Design CMPE 413CMOS BasicsSignal StrengthsSignals such as 1 and 0 have strengths, measures ability to sink or source currentVDD and GND Rails are the strongest 1 and 0Under the switch abstraction, G has complete control and S and D have no effect.In reality, the gate can turn the switch on only if a potential difference of at least Vt exists between the G and S.We will look at Vt in detail later on in the course.Thus signal strengths are related to Vt and therefore p and n transistors produce signals with different strengthsStrong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~GND + Vt).0111*** Strong 0*** Weak 100Weak 0 *** Strong 1***01nMOS pMOSSDSDGG7Principles of VLSI Design CMPE 413CMOS BasicsCMOS InverterTHE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY? VddCMOS InverterP1N1AOutAO0110AOVddN1AOutBAD IDEAP18Principles of VLSI Design CMPE 413CMOS BasicsNAND and NOR CMOS GatesABCABC001011101110ABCABC001010100110VddBOutAP1P2N1N2VddA BOutP1P2N2N19Principles of VLSI Design CMPE 413CMOS BasicsPass TransistorThe off-state of a transistor creates a high impedance condition Z at the drain.No current flows from source to drain. So transistors can be used as switches.However, as we previously discussed this will produce degraded outputs, if only one transistor is used as a switch.gsdg = 0sdg = 1sd0 strong 0Input Output1 degraded 1gsdg = 0sdg = 1sd0 degraded 0Input Outputstrong 1g = 1g = 1g = 0g = 010Principles of VLSI Design CMPE 413CMOS BasicsTransmission GatesP1N1InOutAAOne pMOS and one nMOS in parallel.Note that neither transistor is connected to VDD or GND.A and A control the transmission of a signal on In to Out.Transmission gates act as tristate buffers.g = 0, gb = 1abg = 1, gb = 0ab0 strong 0InputOutput1strong 1ggbababggbabggbabggbg = 1, gb = 0g = 1, gb = 011Principles of VLSI Design CMPE 413CMOS BasicsTransmission Gate Application: Select MuxHow many transistors are required to implement this using CMOS gates?SelectInOutSelectVDDSelectSelectOutABTransmission Gate 2-to-1 MUXSelect Out01BATruth Table for 2-to-1 MUXOut = A.S + B.S12Principles of VLSI Design CMPE 413CMOS BasicsD LatchCLKDQLatchDCLKQPositivelevel-sensitivelatch10DCLKQCLKCLKCLKCLKDQQQIf CLK is unavailable one extra inverter needed to generate it using CLK13Principles of VLSI Design CMPE 413CMOS BasicsD Flip-FlopPositiveedge-triggeredflip-flopFlopCLKDQDCLKQmaster-slaveflip-flopa.k.aQMCLKCLKCLKCLKQCLKCLKCLKCLKDLatchLatchDQQMCLKCLKIf CLK is unavailable one extra inverter needed to generate it using CLK MasterSlaveMaster Slave14Principles of VLSI Design CMPE 413CMOS BasicsD Flip-Flop OperationCLK = 1DCLK = 0QDQMQMQDCLKQQM follows D, Q is latchedQM transferred to Q, QM latched Positiveedge-triggeredflip-flop15Principles of VLSI Design CMPE 413CMOS BasicsMore CMOS GatesVddVddOutP1P2N2N1BA16Principles of VLSI Design CMPE 413CMOS BasicsAnd More CMOS GatesBABOut17Principles of VLSI Design CMPE 413CMOS BasicsAnd More CMOS GatesVddABCDN2N3