Sequential CircuitsSequential CircuitsSequential ElementsSequential Elements: LatchSequential Elements: LatchSequential Elements: LatchSequential Elements: LatchSequential Elements: Flip-FlopSequential ElementsSequential ElementsSequential ElementsTiming DiagramsSequencing MethodsMax-Delay: Flip-FlopsMax-Delay: 2-Phase LatchesMax-Delay: Pulsed LatchesMin-Delay: Flip-FlopsMin-Delay: 2 Phase LatchesMin-Delay: Pulsed LatchesTime BorrowingTime BorrowingTime BorrowingClock SkewClock Skew: Latches1Principles of VLSI Design CMPE 413Sequential CircuitsSequential CircuitsCombinational CircuitsOutputs depend on the current inputsSequential Circuits Outputs depend on current and previous inputs Requires separating previous, current and future Called states or tokens Example: Finite State Machines (FSMs), PipelinesCLclkin outclk clk clkCL CLPipelineFinite State Machine2Principles of VLSI Design CMPE 413Sequential CircuitsSequential CircuitsIf tokens moved through pipeline at constant speed, no sequencing elements will be neededEx: Fibre-optic cable, called wave pipelining in circuitsHowever, dispersion is high in most circuitsWe need to delay fast tokens, so that they don't catch up with slow tokensUse flip-flops to delay fast tokens so that they move through exactly one stage per cycleInevitably adds some delay to slow tokensMakes circuit slower than just the logic delayCalled sequencing overheadSometimes called clocking overheadBut it applies to asynchronous circuits tooInevitable side effect of maintaining sequence3Principles of VLSI Design CMPE 413Sequential CircuitsSequential ElementsLatchLevel sensitiveTransparent latchD latchFlip-FlopEdge triggeredMaster-slave flip-flopD flip-flop, D registerDFlopLatchQclk clkDQclkDQ (latch)Q (flop)4Principles of VLSI Design CMPE 413Sequential CircuitsSequential Elements: LatchPass Transistor LatchPros: Tiny Low clock loadsCons: Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion inputDQφ5Principles of VLSI Design CMPE 413Sequential CircuitsSequential Elements: LatchTransmission Gate Latch No Vt drop Requires inverted clockInverting BufferPros: Restoring No backdriving Fixes either:output noise sensitivityOr diffusion inputCons: Inverted outputDQφφDφφXQDQφφ6Principles of VLSI Design CMPE 413Sequential CircuitsSequential Elements: LatchTristate feedback Static Backdriving riskStatic latches are now essentialBuffered Input Fixes diffusion inputNoninvertingφφφφQDXφφQDXφφ7Principles of VLSI Design CMPE 413Sequential CircuitsSequential Elements: LatchBuffered Output Non backdrivingWidely used in standard cells Very robust (important feature) Rather large Rather slow (1.5 - 2 FO4 delays) High clock loadingDatapath Latch Smaller, faster Unbuffered inputφφQDXφφφφφφQDX8Principles of VLSI Design CMPE 413Sequential CircuitsSequential Elements: Flip-FlopFlip-FlopBuilt as a pair of back-to-back latchesDQφφφφXDφφφφXQQφφφφ9Principles of VLSI Design CMPE 413Sequential CircuitsSequential ElementsEnableIgnore clock when enable is inactiveMux: increase latch D-Q delayClock-gating: increase enable setup time, skewDQLatchDQenenφφLatchDQφ01enLatchDQφ enDQφ01enDQφ enFlopFlopFlopSymbol Multiplexer Design Clock Gating Design10Principles of VLSI Design CMPE 413Sequential CircuitsSequential ElementsResetForce output low when reset is assertedSynchronous vs. asynchronousDφφφφQQφφφφresetDφφφφφφQφφDresetφφQφφDresetresetφφresetSynchronous Reset Asynchronous ResetSymbolFlopDQLatchDQreset resetφφφφQreset11Principles of VLSI Design CMPE 413Sequential CircuitsSequential ElementsSet / ResetSet forces output high when assertedFlip-Flop with asynchronous set and resetDφφφφφφQφφresetsetresetset12Principles of VLSI Design CMPE 413Sequential CircuitsTiming DiagramsFlopAYtpdCombinationalLogicAYDQclkclkDQLatchDQclkclkDQtcdtsetuptholdtccqtpcqtccqtsetuptholdtpcqtpdqtcdqLatch/Flop Hold TimetholdLatch/Flop Setup TimetsetupLatch D-Q Cont. DelaytpcqLatch D-Q Prop DelaytpdqLatch/Flop Clk-Q Cont. DelaytccqLatch/Flop Clk-Q Prop DelaytpcqLogic Cont. DelaytcdLogic Prop. DelaytpdLatch/Flop Hold TimetholdLatch/Flop Setup TimetsetupLatch D-Q Cont. DelaytpcqLatch D-Q Prop DelaytpdqLatch/Flop Clk-Q Cont. DelaytccqLatch/Flop Clk-Q Prop DelaytpcqLogic Cont. DelaytcdLogic Prop. DelaytpdContamination propogation delaysand13Principles of VLSI Design CMPE 413Sequential CircuitsSequencing Methods Flip-Flops  2-Phase latches Pulsed latchesFlip-FlopsFlopLatchFlopclkφ1φ2φpclk clkLatchLatchφpφpφ1φ1φ22-Phase Transparent Latches Pulsed LatchesCombinational LogicCombinationalLogicCombinationalLogicCombinational LogicLatchLatchTcTc/2tnonoverlaptnonoverlaptpwHalf-Cycle 1 Half-Cycle 114Principles of VLSI Design CMPE 413Sequential CircuitsMax-Delay: Flip-FlopsF1F2clkclk clkCombinational LogicTcQ1 D2Q1D2tpdtsetuptpcqTCtpcqtpdtsetup++=tpdTCtsetuptpcq+()−≤sequencing delay15Principles of VLSI Design CMPE 413Sequential CircuitsMax-Delay: 2-Phase LatchesTcQ1L1φ1φ2L2L3φ1φ1φ2CombinationalLogic 1CombinationalLogic 2Q2 Q3D1 D2 D3Q1D2Q2D3D1tpd1tpdq1tpd2tpdq2tpdtpd1tpd2+ Tc2tpdq()−≤=Tctpdq1tpd1tpdq2tpd2++ +≥sequencing delay16Principles of VLSI Design CMPE 413Sequential CircuitsMax-Delay: Pulsed LatchesTcQ1 Q2D1 D2Q1D2D1φpφpφpCombinational LogicL1L2tpw(a) tpw > tsetupQ1D2(b) tpw < tsetupTctpdtpdqtpcqtpdtsetupTCmax tpdqtpdtpcqtpdtsetuptpw−++,+()≥tpdTCmax tpdqtpcqtsetuptpw−+,()−≤sequencing delay17Principles of VLSI Design CMPE 413Sequential CircuitsMin-Delay: Flip-FlopsCLclkQ1D2F1clkQ1F2clkD2tcdtholdtccqtcdtholdtccq−≥18Principles of VLSI Design CMPE 413Sequential CircuitsMin-Delay: 2 Phase LatchesCLQ1D2D2Q1φ1L1φ2L2φ1φ2tnonoverlaptcdtholdtccqtcd1tcd2, tholdtccqtnonoverlap−−≥Hold time reduced by nonoverlapParadox: Hold applies twice each cyclevs. only once for flopsBut flops have two latches !!!19Principles of VLSI Design CMPE 413Sequential CircuitsMin-Delay: Pulsed LatchesCLQ1D2Q1D2φptpwφpL1φpL2tcdtholdtccqtcdtholdtccqtpw+−≥Hold time increased by pulse width20Principles of VLSI Design CMPE 413Sequential CircuitsTime BorrowingIn a flip-flop based system Data launches on one rising/falling edge Must setup before next rising/falling edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edgesIn a latch-based system Data can pass through latch