Delay DefinitionsDelay EstimationRC Delay ModelsRC Delay ModelsRC Delay ModelsRC Delay Models: LayoutsRC Delay Models: Layout ComparisonElmore DelayElmore DelayElmore DelayDelay Components and Contamination Delay1Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationDelay Definitions tpdr: rising propagation delay From input to rising output crossing VDD/2 tpdf: falling propagation delay From input to falling output crossing VDD/2 tpd: average propagation delaytpd = (tpdr + tpdf)/2 tr: rise time From output crossing 20% to 80% VDD tf: fall time From output crossing 80% to 20% VDD tcd: average contamination delay tcd = (tcdr + tcdf)/2 tcdr: rising contamination delay: Min from input to rising output crossing VDD/2 tcdf: falling contamination delay: Min from input to falling output crossing VDD/22Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationDelay EstimationSolving differential equations by hand is hard.SPICE like simulators used for accurate analysis. But simulations are expensive.We need to be able to estimate delay although not as accurately as simulator.Use RC delay models to estimate delay C = total capacitance on the output node Use Effective resistance R Therefore tpd = RCTransistors are characterized by finding their effective R. (V)0.00.51.01.52.0 t(s)0.0 200p 400p 600p 800p 1ntpdf = 66ps tpdr = 83psVinVout3Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationRC Delay ModelsEquivalent circuits used for MOS transistors Ideal switch + capacitance and ON resistance Unit NMOS has resistance R, capacitance C Unit PMOS has resistance 2R, capacitance CCapacitance proportional to widthResistance is inversely proportional to widthkgsdgsdkCkCkCR/kkgsdgsdkCkCkC2R/k4Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationRC Delay ModelsA 3-input NAND gate with transistor widths chosen to achieve effective rise and fall resis-tance equal to that of a unit inverter (R)3 NMOS in series = 3R, therefore each has to be three times the minimum width.3 PMOS(2R) in parallel, worst case one ON, therefore each has to be twice minimum width3322235Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationRC Delay Models3-input NAND gate with it's gate and diffusion capacitances (assuming all nodes are con-tacted). Estimated at the schematic level, values will be different if you look at layouts.2223333C3C3C3C2C2C2C2C2C2C3C3C3C2C2C 2C9C3C3C3332225C5C5CConservative estimate would assume that this twodiffusions are uncontacted and therefore have lower capacitance(the difference is usually ignored for hand calculations)Capacitance can be lower if you look at the layout6Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationRC Delay Models: LayoutsGood layout minimizes diffusion area.NAND3 gate shown below, shares one diffusion contact, thus lowering the output capacitance by 2C. Contacted diffusions are assumed.7C3C3C3332223C2C2C3C3CIsolatedContactedDiffusionMergedUncontactedDiffusionSharedContactedDiffusion7Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationRC Delay Models: Layout ComparisonWhich layout is better?AVDDGNDBYAVDDGNDBY8Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationElmore DelayON transistors are considered as resistors.Pull-up or pull-down networks are considered as RC ladders.Elmore Delay of a RC ladder:tpdRni−Cinodes i∑=R1C1R1R2+()C2… R1R2… RN+++()CN+++=R1R2R3RNC1C2C3CN9Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationElmore DelayRising propagation delay of a 2-input NAND gate driving h identical NAND gates6C2C22224hCBAxYh copiesR(6+4h)CYtpdr64h+()RC=10Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationElmore DelayFalling propagation delay of a 2-input NAND gate driving h identical NAND gatesh copiestpdf2C()R2--- -⎝⎠⎛⎞64h+()C[]R2--- -R2--- -+⎝⎠⎛⎞+=6C2C22224hCBAxY(6+4h)C2CR/2R/2xY74h+()RC=11Principles of VLSI Design CMPE 413Circuit Characterization and Performance EstimationDelay Components and Contamination DelayTotal delay is composed of two parts: Parasitic delay: 6 or 7 RC in previous example, independent of load Effort delay: 4h RC in previous example proportional to load capacitance.Contamination Delay (best case delay): can be substantially less than propagation delay.Example: Both inputs fall simultaneously in 2-input NAND