Complementary CMOSBuilding CMOS Gates (n-side)Building CMOS Gates (p-side)Building CMOS Gates (Final CMOS gate)Useful TransformationsUseful TransformationsTransformation ExamplesTransformation ExamplesUseful Transformations1Principles of VLSI Design CMPE 413CMOS BasicsComplementary CMOSComlementary CMOS Logic Gates: nMOS pull-down network pMOS pull-up network Static CMOS Complementary CMOS gates always pro-duce 1 or 0 Pull-up network is complement (dual) of pull-down networkPull-up OFF Pull-up ONPull-down OFFZ (float) 1Pull-down ON0 X(Crowbar)pMOSpull-upnetworkoutputinputsnMOSpull-downnetwork2Principles of VLSI Design CMPE 413CMOS BasicsBuilding CMOS Gates (n-side)CMOS is inherently inverting.  Gates with expression of the form are easier to build.For making the n-side (pull-down network) use the un-inverted expression. For e.g.: Implement  For n-side use  AND expressions are implemented using series connection of n transistors OR expressions are implemented using parallel connection of n transistorsF ressionexp()=FAB•()CD•()+()=FAB•()CD•()+=ABCDABAB•() CD•()CDAND: Series AND: SeriesAB•()CD•()+OR: Parallel3Principles of VLSI Design CMPE 413CMOS BasicsBuilding CMOS Gates (p-side)For making the p-side (pull-up network) invert the expression used for n-side. For e.g.: Implement  For n-side use (previous slide) For p-side invert above expression: AND expressions are implemented using series connection of p transistors OR expressions are implemented using parallel connection of p transistorsFAB•()CD•()+()=FAB•()CD•()+=FAB+()CD+()•=AB+() CD+()OR: Parallel OR: ParallelAB+()CD+()•AND: SeriesABCDABCD4Principles of VLSI Design CMPE 413CMOS BasicsBuilding CMOS Gates (Final CMOS gate)Combine the n-side (pull-down) and p-side (pull-up) to make the final gate.FAB•()CD•()+()=ABCDABCDF5Principles of VLSI Design CMPE 413CMOS BasicsUseful TransformationsYou must know all the following transformations between levels of abstractions(1) Boolean expression to CMOS transistor schematic Previous analysis shows how to do this step It assumes that the Boolean expression is already in the appropriate form, which may not always be ture.Boolean Expression Reduction You should already know how to manipulate boolean expressions, e.g., using De Morgan's Laws, from exercises in other courses. The objective is to reduce a boolean expression so that it can be realized in full-com-plementary CMOS using the minimum number of transistors. You are not expected to realize CMOS gates using pass structures in which the inputs are used to drive the output of the gate. e.g. (Lecture 2: XOR, XNOR)Boolean expression CMOS transistor-level (with reductions)schematic analysisCMOS layout12346Principles of VLSI Design CMPE 413CMOS BasicsUseful TransformationsThe following heuristics can be applied as target reductions that will help you to obtain minimum realizations: Since CMOS is naturally inverting, you'll want to target a final expression of the form: Many times only uncomplemented literals are available as signals in your circuit. Therefore, the reductions should attempt to remove the complemented literals in the Boolean expression.Application of De Morgan's Laws can be used to transform complemented literals to NANDs and NORs. You should analyze each transformation to learn the trade-offs.F expression()=7Principles of VLSI Design CMPE 413CMOS BasicsTransformation ExamplesLet's try:The following reduction sequence can be applied that targets NANDs and removes the complemented literals: FAB()CD+()E+=FAB()CD+()E+=FABCD+()E•=Invert both sides.How many transistors are needed here?FAB+()CD+()E•=FACD+()EBCD+()E+=Multiply.FACD+()EB CD+()E++=FACD+()EB CD+()E++=FAB+()CD+()E•=Build here?:Or Build here?: 6 for OAI, 8 for B AOI, # transistors: 6 for OAI, 2 forinverter for B, 6 for final OAI.6 for final AOI.Build Inverse : 14 TransistorsFAB()CD+()E+=8Principles of VLSI Design CMPE 413CMOS BasicsTransformation ExamplesNote that further reductions to NANDs and NORs may not pay off in the previous case.In the next case, it is possible to get rid of an uncomplemented literal without increasing the size of the OAI: Further transformations are not useful -- convince yourself.FAB()CD+()E+=FABCD+()E•=Invert both sides.Apply DeMorgan's Laws.FAB+()CD+()E•=FAB+()CD+ E+()=FAB+()CD+()E•=Build here?:# transistors: 6 for OAI, 4 forinverters, 6 for final OAI.FAB()CD+()E+=Or Build here?: 4 for NOR, 2 for inverter, 8 for final OAI.Build Inverse : 16 Transistors9Principles of VLSI Design CMPE 413CMOS BasicsTransformation ExamplesExpressions with repeated variables may be simplified to save a couple transistorsFABCACD+=F ABC ACD+=4 + 2 + 10 + 2FABC+()ACD+()=2 + 4 + 10F AA ACD ABC BCCD+++=BCCD is redundant (covered) by the other terms, e.g, F ACD ABC+=2 + 4 + 10FACD+()ABC+=FACD+()ABC+=6 + 8 ( 14 !)FACDBCACD+()+ ACD BC A ACD+()+==10Principles of VLSI Design CMPE 413CMOS BasicsTransformation ExamplesIn contrast to:FAB()AC+()D+=FAB+()AC+()D=FAB+()AD CD+()=6 for AB NAND, 8 for OAI, 4 for final NAND.FAB()AC+()D+=FAB()AC+()D=FAB+()AD+()CD+()=F AAADABBD+++()CD+()=F ABC ABD ADC ADD BDC BDD+++ ++=F ABC ABD AD BD+++=FABCDAB+()+=F ABC++()DA B+()+=6 for NOR, 2 for inverter, FAB+()AC+()D=8 for OAI, 2 for inverted B, 6 for final OAI.8 for final OAI -- no better thanthe earlier expression.11Principles of VLSI Design CMPE 413CMOS BasicsTransformation ExamplesSometimes it is best to implement the inverse function and add an inverter.For example, Carry, which has all uncomplemented inputs.What about XOR and XNOR?The best way to learn this is through practice.Simply make up an expression of multiple variables and invert a couple of the literals and/or subexpressions.Carry AB CinAB+()+=Carry AB CinAB+()+=FABAB+=FAB+()AB+()=FABAB+=FABAB+()+=FABAB+=How many transistors are needed here?12Principles of VLSI Design CMPE 413CMOS BasicsUseful Transformations(2) Translating from transistor-level schematics to Boolean expressions is straightfor-ward.Simply write the n-tree expression using the rules for series and parallel transistors given earlier. Invert the final expression.(3) Translating from transistor-level schematic diagrams to layout is covered in the labo-ratories.(4) Translating from layout to transistor-level schematic diagrams is also covered in the laboratories. In general, start by identifying the transistor sources connected to VDD or GND