Design MarginDesign MarginDesign MarginDesign MarginDesign MarginReliabilityReliabilityReliabilityReliabilityReliabilityReliabilityScalingScalingScalingInternational Technology Roadmap for Semiconductors (ITRS)Impacts on DesignImpacts on Design1Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingDesign MarginDesign Margin requried as there are three sources of variation- two enviornmental and one manufacturing: Supply Voltage Operating temperature Process variationAim is to design the circuit that will reliably operate over all extremes of these three vari-ables.Variations can be modeled as uniform or normal (Gaussian) statistical distributions.01-11All parts lie withinthe half rangeUniformNormal (Gaussian)01-123-2-3(1σ − 31.7%)(2σ − 4.6%)(3σ − 0.26%)2Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingDesign MarginSupply VoltageSupply voltage may vary due to tolerance of voltage regulators, IR drop along the sup-ply rail and di/dt noise.Typically the supply is specified as +/- 10% around nominal (uniform distribution)Speed is roughly proportional to VDD, also noise budgets are affected.TemperatureParts must operate over a range of temperatures.Standard Minimum MaximumCommercial0oC70oCIndustrial-40oC85oCMilitary-55oC125oC3Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingDesign MarginProcess VariationDevices have variations in film thicknesses, lateral dimensions, doping concentrations etc.The parameters of individual transistors vary from: Lot to lot (interprocess variation) Wafer to wafer (interprocess variation) Die to die (intraprocess variation)Design CornersFrom the designer's point of view, the collective effects of process and environmental variations can be lumped into their effect on transistors: typical (nominal) fast slowSpeed of each type of transistors, interconnect speed variations and environmental varia-tions are used to define design or process corners.4Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingDesign MarginDesign Corners (contd.)Environmental corners (1.8V process)Corner Voltage TemperatureFast (F) 1.980oCTypical (T) 1.870oCSlow (S) 1.62125oCSlowFastNMOSPMOSSlowFastSFFFFSSSTT5Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingDesign MarginDesign corner checksCornerPurposeNMOS PMOS WireVDDTempT T T S S timing specifications (binned parts)T S S S S timing specifications (conservative)F F F F F DC power dissipation, race conditions, hold time constraints, pulse collapse, noiseF F F F S subthreshold leakage noise, overall noise analysisS S F S S races of gates against wiresF F S F F races of wires against gatesS F T F F pseudo-NMOS & ratioed circuits noise margins, memory read/write, race of PMOS against NMOSF S T F F ratioed circuits, memory read/write, race of NMOS against PMOS6Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingReliabilityReliability problems cause integrated circuits to fail permanently, including: Electromigration Self-heating Hot Carriers Latchup Overvoltage failureMean Time Between Failures (MTBF)# devices * hours of operation / # failuresFailures in Time (FIT)The number of failures that would occur every thousand hours per million devices.e.g. 1000 FIT is one failure in 106 hours = 114 years. (good for a single chip !!!)System with 100 chips each rated at 1000 FIT and you have 10 systems,failure rate is 100*1000*10 = 106 FIT, or one failure every 1000 hours (42 days).Need to target 100 FIT !!!7Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingReliabilityMost systems exhibit the bathtub curve.Important to age systems past infant mortality (burn-in) before shipping productsElectromigrationCauses wearout of metal interconnect through the formation of voidsHigh current densities lead to an 'electron wind' that causes metal atoms to migrate over time.FailureRateTimeInfantMortalityUsefulOperatingLifeWearout8Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingReliabilityElectromigration (contd.)Depends on the current density J. Current limits are usually expressed as a maximum Jdc More likely to occur for wires carrying DC currentsContact cuts have lower current density than metal linesSelf-heatingBidirectional wires are less prone to electromigration, their current density is limited by self-heatingHigh current dissipate power, raising in temperature and thus resistance and delayLimited using reasonable values of Jrms In summary, electromigration is primarily a problem in power and ground lines, self-heat-ing limits the RMS current density in bidirectional signal lines. Significant current flows through wire contacting NMOS and PMOS transistors and therefore needs consideration.9Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingReliabilityHot CarriersAs transistors switch, some high energy (hot) carriers may be injected into the gate oxide and become trapped thereDamaged oxides change I-V: increases current in PMOS and decreases current in NMOSHot carriers cause circuit wearout as NMOS transistors become too slowWear is limited by setting maximum values on input rise-time and stage electrical effortThe maximum values depend on process and operating voltageLatchupParasitic bipolar transistors are formed by substrate, well and diffusionIf these transistors turn ON, it develops a low-resistance path between VDD and GND, caus-ing catastrophic meltdown, called latchup.10Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingReliabilityLatchup (contd)The cross-coupled transistors form a bistable silicon-controlled rectifier (SCR)Ordinarily both transistors are off, but latchup can be triggered by transient current during normal chip power-up or external voltages outside the normal operating rangeLatchup can be prevented by minimizing the two resistance values.Can be accomplished by putting one tap (contact) per well, connecting substrate and well taps to the supply using metal lines, placing a tap per 5 transistors and clustering NMOS near GND and PMOS near VDDp+p+n+n+n+p+RwellRsub11Principles of VLSI Design CMPE 413Design Margin, Reliability and ScalingReliabilityOvervoltage failuresTransistors can be easily damaged by overvoltage reliability problems due to: Electrostatic Discharge (ESD): Static electricity entering I/O pads can cause very large voltage and current transients