Inverter layout alternatives:Complex Logic GatesComplex Logic GatesMore Layout ExamplesMore Layout ExamplesMore Layout ExamplesMore Layout Examples1Principles of VLSI Design CMPE 413Layout ExamplesInverter layout alternatives:2Principles of VLSI Design CMPE 413Layout ExamplesComplex Logic Gates"Stacked layout" (on right): signals applied to multiple n- and p-transistors.Works well for cascaded gates.AB CDABSingle unbroken line of diffusion not possible.XNOR3Principles of VLSI Design CMPE 413Layout ExamplesComplex Logic GatesLine of diffusion ruleTransistors form a line of diffusion intersected by poly.Diffusion will be unbroken if identically labeled Euler paths can be found for the p and n trees:CDBAABCDVDDI1I2I3GNDAZZI1I2I3ZBCDLet vertices representsource/drain connections.Let edges representtransistors.For example, A-B-C-D workshere (see previous slide).4Principles of VLSI Design CMPE 413Layout ExamplesMore Layout Examples5Principles of VLSI Design CMPE 413Layout ExamplesMore Layout Examples6Principles of VLSI Design CMPE 413Layout ExamplesMore Layout Examples7Principles of VLSI Design CMPE 413Layout ExamplesMore Layout
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