CMPE 315 LabLAB Assignment #1 for CMPE 315Assigned: Fri, Sep 5thDue: Mon, Sep 15thDescription: Design and Test a simple 8 function 4-bit two's complement ALUwritten using structural VHDL and tested with NC-VHDL.This is a simple exercise in which you will write a VHDL program which describes an arithmeticunit and you will be required to validate it using the nc simulator.Report Requirements:1) Submit the VHDL source code and your test benches (one using file IO and one printing on std-out). We will use the gl submit system for class submissions.2) Describe the simulation procedure in brief.3) Turn in the output showing that the ALU implements the functions required. This will requirean input file and the corresponding output file. Explain which bits corresponds to which input inthe input file and which bits in the output file correspond to which outputs.4) You must use hierarchy in your design specification. In other words, specifying the entiredesign as one entity/architecture will earn 0 points. Your write-up should include a diagram thatshows which entity calls other entities and what functions each entity performs. An example dia-gram is shown below.XYCinnBS0S1nnnCoutG = X + Y + CinS1S000110101Select InputYall 0’sBBall 1’sCin = 0G = X + Y + InCin = 1G = A (transfer)G = A + B (add)G = A + BG = A - 1 (decrement)G = A + 1 (increment)G = A + B + 1G = A + B + 1G = A (transfer)ACMPE 315 Lab5) The major portion of your grade will depend on the correctness of your code. The TA will run aset of tests on your design. In order to make your design file compatible with the test files, youMUST use the following top-level entity and architecture statements EXACTLY as shown below.The bold dots indicate that you must complete that part of the port specification on your own.Failing to follow these instructions will have significant impact on your grade.entity alu_4 isport (A : .... B : .... Cin : .... S0 : ..... S1 : ..... G : ..... Cout : ....... );end alu_4;architecture structural of alu_4 is............end structural;PRINT ALL VHDL CODE USING THE ENSCRIPT COMMAND GIVEN ON THE WEBPAGEAND INCLUDE IT AT THE END OF YOUR REPORT.THE LABS ARE INDIVIDUAL EFFORTS. INSTANCES OF CHEATING WILL RESULT INYOU FAILING THE COURSE.ALUUnit 1Unit 2Unit 3Unit 4:1 Unit 5Input AInput BControl 1 and 2Control 3OutputUnit 1 :- Inverts AUnit 2 :- Modifies A depending on control signal 1 and 2Unit 3 :- Takes input B and performs 2's complimentUnit 4 :1 : - and so on.Unit 4:2Control 3This is just an example and your design won't look the