Combinational CircuitsCombinational CircuitsCombinational CircuitsCombinational CircuitsInput OrderingAsymmetric GatesSkewed GatesSkewed GatesAsymmetric SkewBest P/N RatioCombination Circuit Observations1Principles of VLSI Design CMPE 413Combinational CircuitsCombinational CircuitsLogical Effort of Compound GatesABCDYABCYABCCABABCDACBD22144422224444gA = 6/3gB = 6/3gC = 5/3p = 7/3gA = 6/3gB = 6/3gC = 6/3p = 12/3gD = 6/3YAAYgA = 3/3p = 3/321YYunit inverter AOI21 AOI22ACDEYBYBCADEABCDEgA = 5/3gB = 8/3gC = 8/3gD = 8/32222266663p = 16/3gE = 8/3Complex AOIYABC=+g YABCD=+gg()YABCDE=++ggYA=2Principles of VLSI Design CMPE 413Combinational CircuitsCombinational CircuitsBubble Pushing Start with network of AND/OR gates Convert to NAND/NOR + inverters Push bubbles around to simplify logicDeMorgan's LawY YYDY(a) (b)(c) (d)3Principles of VLSI Design CMPE 413Combinational CircuitsCombinational CircuitsMultiplexer example: Estimate the delay of NAND and compound gate designs of a mux with maximum capacitance of 16 units on each input and an output load of 160 unitsYD0SD1SYD0SD1SH = 160/16 = 10B = 1N = 2 P = 2 + 2 = 4 G = (4/3) * (4/3) = 16/9F = GBH = 160/9P = 4 + 1 = 5 G = (6/3) * (1) = 2F = GBH = 20fˆFN4.5==DNfˆP+ 14τ==fˆFN4.2==DNfˆP+ 12.4τ==4Principles of VLSI Design CMPE 413Combinational CircuitsCombinational CircuitsExample (contd.): Annotate transistor sizes to achieve the above delays66661010Y241210108888888825252525Y1616160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 365Principles of VLSI Design CMPE 413Combinational CircuitsInput OrderingWe were using a very simple delay modelLet's calculate the parasitic delay for Y falling, considering input arrival times i.e. If A arrives latest? If B arrives latest?Outer input is the one closest to the supply rail (B)Inner input is the closest to the output (A)If input arrival times are known, connect the latest input to the inner terminal6C2C2222BAxYWith A arriving the latest the delay is 2τHowever with B arriving the latest the delay is 2.33τ6Principles of VLSI Design CMPE 413Combinational CircuitsAsymmetric GatesAsymmetric gates favor one input over the otherE.g. Suppose input A is the most critical Use smaller transistor on A (less C) Boost size of non-critical input This keeps the total resistance the samegA= 10/9gRESET = 2gTOTAL = gA + gRESET = 28/9Asymmetric gate approaches g=1 on critical input but total logical effort goes upSymmetric gatesInputs can be made perfectly symmetricAresetY44/322resetAYABY2112117Principles of VLSI Design CMPE 413Combinational CircuitsSkewed GatesSkewed gates favor one edge over the otherEx: Rising output of the inverter is the most criticalDownsize the non-critical NMOS transistorDefinition: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition gu = 2.5/3 = 5/6, gd = 2.5/1.5 = 5/3Skewed gates reduce size of non-critical transistorsLogical effort is smaller for preferred direction but larger for the other direction1/22AY12AY1/21AYHI-skewinverterunskewed inverter(equal rise resistance)unskewed inverter(equal fall resistance)8Principles of VLSI Design CMPE 413Combinational CircuitsSkewed Gates1/22AYInverter1122BAYBANAND2 NOR21/21/244HI-skewLO-skew11AY2211BAYBA1122gu = 5/6gd = 5/3gavg = 5/4gu = 4/3gd = 2/3gavg = 1gu = 1gd = 2gavg = 3/2gu = 2gd = 1gavg = 3/2gu = 3/2gd = 3gavg = 9/4gu = 2gd = 1gavg = 3/2YY12AY2222BAYBA1144unskewedgu = 1gd = 1gavg = 1gu = 4/3gd = 4/3gavg = 4/3gu = 5/3gd = 5/3gavg = 5/3Y9Principles of VLSI Design CMPE 413Combinational CircuitsAsymmetric SkewCombine asymmetric and skewed gatesDownsize non-critical transistors on unimportant inputReduce parasitic delay for critical inputAresetY44/321resetAY10Principles of VLSI Design CMPE 413Combinational CircuitsBest P/N RatioWe have been selecting the P/N ratio to obtain unit rise and fall resistance (2-3 for inverter)Alternative: choose ratio for least average delayEg: Inverter delay, driving an identical inverter (µ = P/N ratio)tpdf = (P + 1)tpdr = (P + 1) (µ/P)tpd = (P + 1) (1 + µ/P) / 2 = (P + 1 + µ + µ/P) / 2Differentiate wrt P, least delay for In general, best P/N ratio is sqrt of that giving equal delay Only improves average delay slightly for inverters But significantly reduces both area and power1PAPµ=Inverter NAND2 NOR211.414AY2222BAYBA1122fastestP/N ratiogu = 1.15gd = 0.81gavg = 0.98gu = 4/3gd = 4/3gavg = 4/3gu = 2gd = 1gavg = 3/2Y11Principles of VLSI Design CMPE 413Combinational CircuitsCombination Circuit ObservationsFor speed: NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving inputFor area and power: Many simple stages vs. fewer high fan-in