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UMBC CMPE 315 - VHDL Tutorial

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CMPE 315 CADENCE TUTORIALPrepared by :- Chintan Patel Page 1VHDL TutorialCadence Setup To run cadence tools you will use your gl accounts. There is one dedicated cadence server oncampus and various labs in the ITE building. The cadence server is:Linux Server:cadence2.gl.umbc.eduEdit the file called .cshrc which is located in your home directory. Type the following line in thefile and save it. source /afs/umbc.edu/software/cadence/etc/setup_2008/cshrc.cadenceVHDL SetupThe steps provided here are for new students who haven’t used cadence before. If you arefamiliar with cadence or have the setup already done you can customize your VHDL work library.Some instructors might require you to perform a different directory setup for their classes. Most ofthe details below should hold true in any of the above cases. This tutorial will cover the steps involved in compiling, elaborating and simulating VHDLdesign files. The NC-simulator under the cadence distribution will be used for this purpose. Thistutorial will cover only the command line option of running all these tools.The first step is to copy some files required to provide library information to the tools. Make adirectory called cadence in your home directory. Make a directory called vhdl inside cadence.Copy the two setup files cds.lib and hdl.var into the cadence directory. cp /afs/umbc.edu/software/cadence/etc/setup_2008/cds.lib ~/cadence/ cp /afs/umbc.edu/software/cadence/etc/setup_2008/hdl.var ~/cadence/VHDL Example filesAfter you have copied these files in your cadence directory you are ready to enter VHDL code.This tutorial will cover the design and simulation of an inverter in VHDL. The code for theinverter is shown below. The emacs editor under most machines has a special vhdl options menuwhen you edit any .vhd file. This will be a great help when learning VHDL as most of the defaultVHDL statements are present in the menu.inverter.vhd file for the inverter.- -- - Entity: inverter- - Architecture : structural- - Author: cpatel2- - Created On: 10/20/00 at 13:32- -CMPE 315 CADENCE TUTORIALPrepared by :- Chintan Patel Page 2-- These are the standard libraries that you are defining.library IEEE;use IEEE.std_logic_1164.all;-- Keep the entity name same as the file name as it will be easier during compilation.-- Ports are the inputs and outputs from your circuit.entity inverter isport (input : in std_logic;output : out std_logic);end inverter;-- Define an architecture for the inverter entity which is either functional or behavioral.architecture structural of inverter isbegin-- Concurrent assignment statement. output <= not (input);end structural; Now before we go on to compiling and simulating we need to make a test bench to test thecode that we just entered. A test bench is another VHDL file that uses your design file and gives itinputs and checks the outputs. The input and output is done using text files through the VHDLcode using inbuilt I/O functions. The test bench file is also shown below.inverter_test.vhd file for the test bench.- -- - Entity: inverter_test- - Architecture : vhdl- - Author: cpatel2- - Created On: 10/20/00 at 01:55- -- - Define the libraries that you are going to use. The two textio libraries define your input and- - output functionslibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_textio.all;CMPE 315 CADENCE TUTORIALPrepared by :- Chintan Patel Page 3use STD.textio.all;- - The entity name here is also the name as the file name.- - The circuit has no ports because this is a test bench file that you are using to test the inverter.entity inverter_test isend inverter_test;- - Define an architecture for the inverter_test entity.architecture test of inverter_test is- - Define the inverter as a component that you will use in this file. The port list is the same as- - the original port list of the inverter entity.component inverter port ( input : in std_logic; output : out std_logic);end component;- - Define an instance of the inverter that you are going to use in this file.for i1 : inverter use entity work.inverter(structural); signal ip,op : std_logic; signal clock : std_logic;begin- - Assign inputs and outputs to the various inverter ports.i1 : inverter port map (ip,op);- - Control the inputs to the circuit.clk : process begin -- process clk clock<=’0’,’1’ after 5 ns; wait for 10 ns; end process clk;- - Read inputs from a input file called inverter_in.txt and write outputs to inverter_out.txtio_process: process file infile : text is in "inverter_in.txt"; file outfile : text is out "inverter_out.txt"; variable ip1,op1 : std_logic;CMPE 315 CADENCE TUTORIALPrepared by :- Chintan Patel Page 4 variable buf : line;begin while not (endfile(infile)) loop readline(infile,buf); read (buf,ip1); ip<=ip1; wait until falling_edge(clock); op1:=op; write(buf,op1); writeline(outfile,buf); end loop; wait;end process io_process;end test; After creating the circuit file for the inverter and the test bench to test the same we are nowready to compile and simulate the circuit. But first we need to create the inverter_in.txt file thatspecifies the input sequences that will be assigned to the inputs to the circuit. This file is created inthe same directory as your code directory. The file should have one sequence per line. In our casethe sequences will only be a single bit sequence because we have a single bit input. Theinverter_in.txt file is shown below.inverter_in.txt file000110101The sequence are assigned arbitrarily. The inverter_out.txt file will be generated automaticallyin the same directory as your code directory when you simulate the circuit. As the circuit we haveimplemented is a simple inverter the inverter_out.txt file would look like the one shown below.inverter_out.txt fileCMPE 315 CADENCE TUTORIALPrepared by :- Chintan Patel Page 511100101The last file required is a run file that provides


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