CMOS TechnologiesN-Well ProcessN-Well ProcessN-Well ProcessN-Well ProcessDesign RulesManufacturing Issues and related rulesCMOS Process EnhancementsCMOS Process EnhancementsCMOS Process EnhancementsCMOS process EnhancementsCMOS process EnhancementsCMOS process Enhancements1Principles of VLSI Design CMPE 413CMOS ProcessingCMOS Technologies n-well process p-well process twin-well process triple-well process silicon on insulatorFabrication Steps (n-well process)p substrateSiO2Spin on the photoresist. Exposed to UV light using the n-well mask. (Photolithography) Blank wafer covered with a layer of SiO2 using oxidationp substrateSiO2Photoresist2Principles of VLSI Design CMPE 413CMOS ProcessingN-Well Processp substrateSiO2PhotoresistStrip off the exposed photoresist using organic solventsp substrateSiO2PhotoresistEtch the uncovered oxide using HF (Hydroflouric acid) p substrateSiO2Etch the remaining photoresist using a mixture of acidsn wellSiO2n-well is formed using either diffusion or ion implantation3Principles of VLSI Design CMPE 413CMOS ProcessingN-Well ProcessStrip off remaining oxide using HF. Subsequent steps use the same photolithography processDeposit thin layer of oxide. Use CVD to form poly and dope heavily to increase conductivityPattern poly using the previously discussed photolithography processCover with oxide to define n diffusion regionsp substraten wellThin gate oxidePolysiliconp substraten wellp substrateThin gate oxidePolysiliconn wellp substraten well4Principles of VLSI Design CMPE 413CMOS ProcessingN-Well ProcessPattern oxide using n+ active mask to define n diffusion regionsDiffusion or ion implantation used to create n diffusion regionsStrip off the oxide to complete patterning stepSimilar steps used to create p diffusion regionsp substraten welln wellp substraten+n+ n+n wellp substraten+n+ n+p substraten welln+n+ n+p+p+p+5Principles of VLSI Design CMPE 413CMOS ProcessingN-Well ProcessCover chip with thick field oxide and etch oxide where contact cuts are neededLayout (mask) view of the inverter.p substrateThick field oxiden welln+n+ n+p+p+p+p substrateMetalThick field oxiden welln+n+ n+p+p+p+GND VDDYAsubstrate tapwell tapnMOS transistorpMOS transistorRemove excess metal leaving wiresMasksNwellpolyN+P+contactsmetal 16Principles of VLSI Design CMPE 413CMOS ProcessingDesign RulesMain objective of design rules is to build reliably functional circuits in as small an area as possible.They represent a compromise between performance and yield More conservative rules increase probability of correct circuit function More aggressive rules increase circuit performanceTwo approaches used Lambda based rules: Also known as scalable rules as they allow first order scalingMoving from one process to another requires only a change in λ.Worked well for 4µm down to 1.2 µm processes.In general, process rarely shrinks uniformly. Micron based rules: All minimum sizes and spacings specified in microns.Rules don't have to be multiples of λ.Can result in 50% reduction in area over λ based rulesStandard in industry.7Principles of VLSI Design CMPE 413CMOS ProcessingManufacturing Issues and related rulesAntenna Rules: Specify maximum area of metal that can be connected to a gateWhen metal wire contacted to transistor gate is plasma etched, it can charge up to a sufficient voltage to break down thin gate oxides.Metal can be contacted to diffusion to provide a path for the charge to bleed away.Violations can be fixed by using diffusion diodes or by shortening the metal segments.Layer Density Rules: Specify minimum and maximum density of particular layer within a specified area.Required to achieve uniform etch rates when using the CMP process.For e.g. a metal layer might have a 30% minimum and 70% maximum fill with a1mm by 1mm area.Resolution Enhancement Rules: Some resolution enhancement techniques discussed before impose additional rulesFor e.g. polysilicon gates should be drawn in a single orientation (horizontal or verti-cal)Modern design tools, can check for rules violations and also fix most of them automati-cally.8Principles of VLSI Design CMPE 413CMOS ProcessingCMOS Process EnhancementsTransistors Multiple threshold voltages and oxide thicknessesProcesses offer multiple threshold voltagesLow threshold devices: faster, higher leakage. High threshold devices: oppositeThin oxides: provide high ON currents but cannot handle high voltages (e.g. I/Os)Thicker oxides provided for I/O devices Silicon on InsulatorAs the name suggests transistors are fabricated on an insulator (SiO2 or sapphire)Insulating substrate eliminates capacitance between the source/drain and body, higher speed devices and low leakage currents.n+ n+ p+ p+npSapphireN transistorP transistorn+ n+ p+ p+npSubstrateN transistorP transistorBuried Silicon Oxide (BOX)9Principles of VLSI Design CMPE 413CMOS ProcessingCMOS Process EnhancementsTransistors (contd.) High-k gate dielectricsTransistors need high gate capacitance to attract charge to the channelThin gates and therefore high gate leakagesThicker gates that leak less can be made with high-k materialse.g. hafnium oxide (k=20), zirconium oxide (k=23), silicon nitride (k=6.5-7.5)Applied using ALD, MOCVD (metallo-organic CVD) or sputtering. Low leakage transistorsScaling transistors causes exponential increase in subthreshold leakagesCan be improved using gate structure where gates is placed on more than one side of the channelWidth is defined bythe height of the fin.gate oxideThese devices are genericallycalled finfets10Principles of VLSI Design CMPE 413CMOS ProcessingCMOS Process EnhancementsTransistors (contd.) Higher mobilityAchieved by using SiGe (silicon germanium) for bipolar transistors in the same conventional CMOS processSilicon Germanium can also be used to improve speed by creating strained silicon Plastic transistorsMOS transistors fabricated with organic chemicalsUsed only for very specific applications as devices are very inexpensive to manu-facture High-voltage transistorsHigh voltage MOSFETs can be integrated onto conventional CMOS processes for switching and high-power applications.Specialized process steps required to achieve very high breakdown voltages.11Principles of VLSI Design CMPE 413CMOS ProcessingCMOS process EnhancementsInterconnect Copper Damascene processUsing copper (higher conductivity) as interconnect instead of aluminum.Several challenges due to copper atom diffusion, etching