riscVsCiscEvolution of ISAsInstruction set architectures have changed over computergenerations with changes in the• cost of the hardware• density of the hardware• design philosophy• potential performance gainsOne way to characterize ISAs:• number of addresses/instruction• regularity of instruction formats• number of addressing modesriscVsCiscNumber & Type of Operands/InstructionOne address & an implied accumulator register• hardware was expensive• accumulator architecture: EDSAC (1949)load AddressB # accum = Memory[AddressB]add AddressC # accum = accum + Memory[AddressC]store AddressA # Memory[AddressA]= accumOne address & a few special purpose registers• extended accumulator (special-purpose register) architecture:Intel 8086• registers for:• data• addresses• segment pointers• special, e.g., PCriscVsCiscNumber & Type of Operands/InstructionGeneral-purpose registers• register-memory architectures• one operand is in memory: IBM 360 (1964)add reg10, AddressA• memory-memory architectures• all operands can be in memory: VAX 780 (1977)add AddressA, AddressB, AddressC• load-store architectures• CDC 6600 (1963), Cray 1• current RISCs (1982 and on)One address & no registers• stack architectures: Burroughs 5000, Intel 8087• use the top of the stack for other, implied operandspush AddressC # increment stack pointer # TOS = Memory[AddressB] push AddressB # do it again add # add top 2 locations; result on TOS] pop AddressA # Memory[AddressA] = TOS # decrement stack pointerriscVsCiscRegularity of Instruction FormatsStartedwith1format(!)• for ease of programming (programming on the binary level!)Then 3 or 4 formats, not necessarily the same length• assembly language & compilers made programming easierMore formats & encoding of variable length instructions• small, low density, expensive memory• CPU-to-memory bottleneck• ISAs reflected high-level language operationsBack to fixed length instructions, few formats• memory is large & cheap• simple encoding facilitates faster hardware interpretation ofinstructionsriscVsCiscCISC Instruction FormatsLots of instruction formats• IBM 360: 5• Intel x86: lots, in part due to lots of addressing modes• Digital VAX: also lots• orthogonal design: all opcodes can be used with anyaddressing mode & any information unitInstructions have varying lengths• IBM 360: instructions can be 2,4 or 6 bytes• Intel x86:, 1 to 17 bytes• Digital VAX: 1 to 54 bytesriscVsCiscIBM 360 FormatsRR format: [ opcode ][R1][R2]r1 <- r1 op r2RX format: [ opcode ][R1][X2][B2][displ]r1 <- r1 op mem[x2+b2+displ]RS format: [ opcode ][r1][r3][b2][displ]mem[b2+displ] <- r1 op r3SI format: [ opcode ][value][b2][displ]mem[b2+displ] <- mem[b2+displ] op valueSS format: [ opcode ][count][r1][addr][r2][addr2]mem[addr2+r2+i] <- mem[addr1+r1+i], 0 <=i<countriscVsCiscAddressing ModesStart with immediate, direct, indirect (or deferred)indirect: register contains the address of the operandThen index registersspecial registers for an array indexThen index + baseallow the sum of 2 registers to be an addressEven more....riscVsCiscVAX Addressing ModesImmediatedifferent addressing modes for constants of different sizesdifferent addressing modes for data and addressconstantsRegister: regthe register contains the operandRegister deferred: (reg)the register contains the address of the operandAutoincrement: (reg)+the register contains the address of the operand & isincremented by the size of the operandafterit’s accessedAutodecrement:-(reg)the address in the register is decrementedbeforethe accessAutoincrement deferred: @(reg)+address in the register is apointerto the address of theoperand & is incremented by the size of the operandPC-relative:both regular & deferredriscVsCiscVAX Addressing ModesDisplacement: displ(reg)separate addressing modes for each information unit which isstored only in the number of bits needed & then sign extendedboth regular & deferredIndexed:used in conjunction with other addressing modesthe contents of the index register is multiplied by the size ofthe operand in bytes & added to the contents of the otherregister• register deferred indexed: (reg)[IndexReg]• autoincrement indexed: (reg)+[IndexReg]• autodecrement indexed: -(reg)[IndexReg]• autoincrement deferred indexed: @(reg)+[IndexReg]• displacement indexed: displ(reg)[IndexReg]• displacement deferred indexed:{@displ(reg)}[IndexReg]add the displacement & the contents of reg to form apointer to the base address (the address where the baseaddress is stored); the base address is fetched & addedto the adjusted index in IndexReg to form the operandaddress; the operand is then fetchedriscVsCiscriscVsCiscIntel x8685% of the microprocessors in the world (not countingembedded processors)Only 8 GPRs (other registers are special purpose)Register-memory architecture• 2 operand instructions; 1 is both source & destination• Addressing relies on segments (code, stack & static data)String instructions in addition to computation, data transfer,controlCondition codes instead of condition registersNo regularity in the ISA• ISA for 8 bits & an extended ones for 16, 32 & 64 bits• Lots of addressing modes (but fewer than the VAX)• some can’t use certain registers• Variable length instructions, variable length opcodes(later)• addresses in bytes, not instructions• Encoding is complicated (see Figure 3.35)riscVsCiscRISC Vs. CISCRISCgeneral philosophy:simple instructions execute faster than complexinstructions•lesstodo• fewer choices; therefore it takes less time to decidewhat is being executed now (smaller circuitry)•simplicity leads to regularityin the hardware design easier toget the hardware right & to debug it• use simple instructions as building blocks for more complexoperations• short cycle time & single-cycle instructions; therefore moreinstructions executed per time unit• few instructions, simple instructions• few addressing modes• fixed-length instructions (32 bits)• few instruction formats: (almost) fixed fields within aninstruction• load/store architecture• hardwired control• conducive to pipelining because each instruction takesabout the same amount of time to execute(later)• expose the implementation to the compiler/programmerriscVsCiscRISC Vs. CISCCISCgeneral philosophy:get faster execution by having a better match between thehigh-level operations & the hardware operationsdirect execution
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