CSE378 Midterm ReviewMIPS ISAMore MIPSALU Bit-sliceLoad WordDecoding SWMulticycle MIPS01/14/19 CSE378 Review 1CSE378 Midterm Review•Moore’s Law -- What are the two versions?•Is Moore’s Law a law?•Explain what an instruction set architecture is [ISA]•What do the terms RISC and CISC mean?01/14/19 CSE378 Review 2MIPS ISA•Give the uses of the fields of an R-type instruction:• [31-26], [25-21], [20-16], [15-11], [10-6], [5-0]•Give the numbers of two registers whose use is specified in the ISA•Give the numbers of two registers whose use is agreed-on by programming language convention•Give the numbers of two registers whose use is agreed-on by programming convention•Explain big-endian and little-endian memory layout01/14/19 CSE378 Review 3More MIPS•Explain the difference between instructions performing “signed” and “unsigned” arithmetic•Explain the operation of the MIPS memory operations: Load and Store•What is a “pseudo-op” or “pseudo instruction”?•How is it that the add and subtract instructions can have the same opcode?•Explain how to load a full word constant into register $401/14/19 CSE378 Review 4ALU Bit-slice•Give the controlsignals for NOR•What value does“Less” get assigned?•Write a poem aboutthe beauty of 2s-complement math01/14/19 CSE378 Review 5Load Word•Give thecontrol linesettings forLW01/14/19 CSE378 Review 6Decoding SW•Explain what changes if SW’s opcode were 110000, and the “don’t cares” were to be 1Signal R-type lw sw beqOp5 0 1 1 0Op4 0 0 0 0Op3 0 0 1 0Op2 0 0 0 1Op1 0 1 1 0Op0 0 1 1 0RegDest 1 0 X XALUSrc 0 1 1 0MemtoReg 0 1 X XRegWrite 1 1 0 0MemRead 0 1 0 0MemWrite 0 0 1 0Branch 0 0 0 1ALUOp1 1 0 0 0ALUOp0 0 0 0 1ORANDOp5Op4Op3Op2Op1Op0AND AND ANDRegDstALUSrcMemtoRegRegWriteMemReadMemWriteBranchALUOp1ALUOp0OR01/14/19 CSE378 Review 7Multicycle MIPS•Explain purpose of MDR•Give control for 2nd cycle•Explain purpose of MDR•Give control for 2nd
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