ReviewSlide 2Slide 3Slide 4Slide 5Slide 6Translation Buffers (TLBs)TLB organizationSlide 9From virtual address to memory location (highly abstracted; revisited)Address translationTLB ManagementTLB management (continued)Paging systems -- Hardware/software interactionsPage fault detection (simplified)Page fault handler (simplified)Completion of page faultTwo extremes in the memory hierarchyOther extreme differencesSome optimizations01/13/19 CSE378 Virtual Mem. Impl. 1Review•What are the advantages/disadvantages of pages versus segments?01/13/19 CSE378 Virtual Mem. Impl. 2Review•What are the advantages/disadvantages of pages versus segments?•What information does a page table entry (PTE) contain? Be complete.01/13/19 CSE378 Virtual Mem. Impl. 3Review•What are the advantages/disadvantages of pages versus segments?•What information does a page table entry (PTE) contain? Be complete.•Every address, virtual or physical, is composed of two parts; what are they?01/13/19 CSE378 Virtual Mem. Impl. 4Review•What are the advantages/disadvantages of pages versus segments?•What information does a page table entry (PTE) contain? Be complete.•Every address, virtual or physical, is composed of two parts; what are they?•In caching terms, what is the main memory?01/13/19 CSE378 Virtual Mem. Impl. 5Review•What are the advantages/disadvantages of pages versus segments?•What information does a page table entry (PTE) contain? Be complete.•Every address, virtual or physical, is composed of two parts; what are they?•In caching terms, what is the main memory?•On a L1 cache miss, the processor stalls, but on a page fault (page miss) it switches context. Why?01/13/19 CSE378 Virtual Mem. Impl. 6Review•What are the advantages/disadvantages of pages versus segments?•What information does a page table entry (PTE) contain? Be complete.•Every address, virtual or physical, is composed of two parts; what are they?•In caching terms, what is the main memory?•On a L1 cache miss, the processor stalls, but on a page fault (page miss) it switches context. Why?•Paging, VM, demand loading are interacting ideas; explain each.01/13/19 CSE378 Virtual Mem. Impl. 7Translation Buffers (TLBs)•To perform virtual to physical address translation we need to look-up a page table entry•Since the page table is in memory, need to access memory–Much too time consuming; 50 cycles or more per memory reference•Hence we need to cache the page tables•For that purpose special caches named translation buffers are part of the memory system–Also named Translation Lookaside Buffers (TLBs)01/13/19 CSE378 Virtual Mem. Impl. 8TLB organization•TLB organized as caches•Therefore for each entry in the TLB we’ll have–a tag to check that it is the right entry–data which instead of being the contents of memory locations, like in a cache, will be a page table entry (PTE)•TLB’s are smaller than memory caches–32 to 128 entries–from fully associative to direct-mapped–there can be an instruction TLB, a data TLB and also distinct TLB’s for user and system address spaces01/13/19 CSE378 Virtual Mem. Impl. 9TLB organizationOffsetVirtual page numberIndextagPhysical frame numberv dprotCopy of PTE01/13/19 CSE378 Virtual Mem. Impl. 10From virtual address to memory location (highly abstracted; revisited) ALUVirtual addressTLBPhysical addresshitcacheMain memorymisshitmissWhy is it called a translation lookaside buffer?01/13/19 CSE378 Virtual Mem. Impl. 11Address translation•At each memory reference the hardware searches the TLB for the translation–TLB hit and valid PTE the physical address is passed to the cache–TLB miss, either hardware or software (depends on implementation) searches page table in memory.•If PTE is valid, contents of the PTE loaded in the TLB and back to step above•In hardware the TLB miss takes 10-100 cycles•In software takes up to 100 -1000 cycles•In either case, no context-switch–Context-switch takes more cycles than a TLB miss•If PTE is invalid, we have a page fault (even on a TLB hit)01/13/19 CSE378 Virtual Mem. Impl. 12TLB Management•TLBs are organized as caches–If small, can be fully associative–Current trend: larger (about 128 entries); separate TLB’s for instruction and data; Some part of the TLB reserved for system–TLBs are write-back. The only thing that can change is dirty bit + any other information needed for page replacement algorithm (cf. CSE 451)•MIPS 3000 TLB (old)–64 entries: fully associative. “Random” replacement; 8 entries used by system–On TLB miss, we have a trap; software takes over but no context-switch01/13/19 CSE378 Virtual Mem. Impl. 13TLB management (continued)•At context-switch, the virtual page translations in the TLB are not valid for the new task–Invalidate the TLB (set all valid bits to 0) –Or append a Process ID (PID) number to the tag in the TLB. When a new task takes over, the O.S. creates a new PID.–PID are recycled and entries corresponding to “old PID” are invalidated.01/13/19 CSE378 Virtual Mem. Impl. 14Paging systems -- Hardware/software interactions•Page tables–Managed by the O.S.–Address of the start of the page table for a given process is found in a special register which is part of the state of the process–The O.S. has its own page table–The O.S. knows where the pages are stored on disk•Page fault–When a program attempts to access a location which is part of a page that is not in main memory, we have a page fault01/13/19 CSE378 Virtual Mem. Impl. 15Page fault detection (simplified)•Page fault is an exception•Detected by the hardware (invalid bit in PTE either in TLB or page table)•To resolve a page fault takes millions of cycles (disk I/O)–The program that has a page fault must be interrupted•A page fault occurs in the middle of an instruction–In order to restart the program later, the state of the program must be saved and instructions must be restartable (precise exceptions)•State consists of all registers, including PC and special registers (such as the one giving the start of the page table address)01/13/19 CSE378 Virtual Mem. Impl. 16Page fault handler (simplified)•Page fault exceptions are cleared by an O.S. routine called the page fault handler which will–Grab a physical frame from a free list maintained by the O.S.–Find out where the faulting page resides on disk–Initiate a read for that page–Choose a
View Full Document
Unlocking...