12/11/2005 CSE 378 I/O 1Page TableConstraints32 bit addresses4KB pages1 wd Page Table EntriesQ1: How big is the program’s data space, probably?Q2: What physical frame holds virtual program page 1?Page Tablev d pro physPGaddr0 0 urw 0x00ab50 0 urw 0x291020 0 urw 0x42fc30 0 ur 0x00ab60 0 ur 0x2111d Pg Table Base Addr:12/11/2005 CSE 378 I/O 2Be A TLBQ3: The Virtual Address 000013a4 is what physical address?Pg Num Pg Offset00001 3a4 Virtual Addr00ab6 3a4 Phys AddrTLB for translation1: 1 0 ur 00ab6Page Tablev d pro physPGaddr0 0 urw 0x00ab50 0 urw 0x291020 0 urw 0x42fc31 0 ur 0x00ab61 0 ur 0x2111d Pg Table Base Addr:12/11/2005 CSE 378 I/O 3ExercisesGive Physical Addresses for these virtual addresses:Q4: 0x 00002000Q5: 0x 00000abcQ6: 0x 00004444Q7: 0x 00004fffQ8: 0x 00003batPg Table Base Addr:Page Tablev d pro physPGaddr0 0 urw 0x00ab50 0 urw 0x291020 0 urw 0x42fc31 0 ur 0x00ab61 0 ur 0x2111d12/11/2005 CSE 378 I/O 4Handling a TLB MissHardware usually handles a TLB miss. How?• Using the V page number, multiply by 4 (e.g. shift 2)• Add result to page table base address stored in an OS-accessible register to get physical addr of PTE• In parallel, pick TLB entry to evict, writing back to page table, if necessary– How to decide if write back is needed?– Eviction Policy– Finding the PTE to write back into• In parallel check that V page number is < the number of mapped pages, i.e. less than pg tab length• If valid PTE load into empty TLB slot, and restart12/11/2005 CSE 378 I/O 5Example• Page Table Base Address:0x 00001444 Len: 5• Handling a miss on V addr 0x 00001000– Say TLB42is not valid; pick it– 00001 x 4 == 00004– 01444 + 00004 == 01448– 00001 < 5 == TRUE– TLB42= 1 0 ur 00ab600001444:Page Tablev d pro physPGaddr0 0 urw 0x00ab50 0 urw 0x291021 0 urw 0x42fc31 0 ur 0x00ab61 0 ur 0x2111d12/11/2005 CSE 378 I/O 6Input-output• I/O is very much architecture/system dependent• I/O requires cooperation between– processor that issues I/O command (read, write etc.)– buses that provide the interconnection between processor, memory and I/O devices– I/O controllers that handle the specifics of control of each device and interfacing– devices that store data or signal events12/11/2005 CSE 378 I/O 7Basic (simplified) I/O architectureCPUCacheM.Cont. D.Cont. N.InterfaceMain memoryDisks NetworkBus12/11/2005 CSE 378 I/O 8Types of I/O devices• Input devices– keyboard, mouse• Output devices– screen, line printer• Devices for both input and output– disks, network interfaces12/11/2005 CSE 378 I/O 9An important I/O device: the disktracksectorDisk surfaceRead-write headsplattersCylinder12/11/2005 CSE 378 I/O 10Secondary memory (disks)• Physical characteristics– Platters (1 to 20) with diameters from 1.3 to 8 inches (recording on both sides)– Tracks (1,000 to 10,000)– Cylinders (all the tracks in the same position in the platters)– Sectors (e.g., 128-256 sectors/track with gaps and info related to sectors between them; typical sector 512 bytes)– Current trend: constant bit density, i.e., more info (sectors) on outer tracks12/11/2005 CSE 378 I/O 11Example: IBM Ultrastar 146Z10• Disk for server– 146 GB– 8 MB cache– 10,000 RPM– 3 ms average latency– Up to 6 platters; Up to 12 heads– Average seek latency 4.7 ms– Sustained transfer rate 33-66 MB/s12/11/2005 CSE 378 I/O 12Disk access time• Arm(s) with a reading/writing head• Four components in an access:– Seek time (to move the arm on the right cylinder). From 0 (if arm already positioned) to a maximum of 15-20 ms. Not a linear function. Smaller disks have smaller seek times.Ultrastar example: Average seek time = 4.7 ms; • My guess: track to track 0.5 ms; longest (inner most track to outer most track) 8 ms– Rotation time (on the average 1/2 rotation). At 3600 RPM, 8.3 ms. Current disks are 3600 (rarely now) or 5400 or 7200 or 10,000 (e.g., the Ultrastar, hence average is 3 ms) or even 15000 RPM12/11/2005 CSE 378 I/O 13Disk access time (ct’d)– Transfer time depends on rotation time, amount to transfer (minimal size a sector), recording density, disk/memory connection. Today, transfer time occurs at 10 to 100 MB/second– Disk controller time. Overhead to perform an access (of the order of 1 ms)– But … many disk controllers have a cache that contains recently accessed sectors. If the I/O requests hits in the cache, the only components of access time are disk controller time and transfer time (which is then of the order of40-100 MB/sec). Cache is also used to prefetch on read.12/11/2005 CSE 378 I/O 14Improvements in disks• Capacity (via density). Same growth rate as DRAMs• Price decrease has followed (today $2-$10/GB?)• Access times have decreased but not enormously– Higher density -> smaller drives -> smaller seek time– RPM has increased 3600 upto 15,000– Transfer time has improved • CPU speed - DRAM access is one “memory wall”• DRAM access time - Disk access time is a “memory gap”– Technologies to fill the gap have not entirely succeeded (currently the most promising is more DRAM backed up by batteries and Flash memory to supercede disk cache)12/11/2005 CSE 378 I/O 15Connecting CPU, Memory and I/OCPUCacheCPU-Memory busI/O busBus adapterMain memoryI/O contr. I/O contr. I/O contr.disk GraphicsNetwork12/11/2005 CSE 378 I/O 16Buses• Simplest interconnect– Low cost: set of shared wires– Easy to add devices (although variety of devices might make the design more complex or less efficient -- longer bus and more electrical load; hence the distinction between I/O buses and CPU/memory buses)– But bus is a single shared resource so can get saturated(both physically because of electrical load, and performance-wise because of contention to access it )• Key parameters:– Width (number of lines:data, addresses, control)– Speed (limited by length and electrical load)12/11/2005 CSE 378 I/O 17Memory and I/O buses• CPU/memory bus: tailored to the particular CPU– Fast (separate address and data lines; of course separate control lines)– Often short and hence synchronous (governed by a clock)– Wide (64-128 and even 256 bits)– Expensive• I/O bus: follows some standard so many types of devices can be hooked on to it– Asynchronous (hand-shaking protocol)– Narrower12/11/2005 CSE 378 I/O 18Bus transactions• Consists of arbitration and commands– Arbitration: who is getting control of the bus– Commands: type of
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