Drawbacks of single cycle implementationAlternative to single cycleMultiple cycle implementationInstruction fetchInstruction decode and read source registersALU executionMemory access or ALU completionLoad completionStreamlining of resourcesFloorPlan for Multicycle MIPSControl Unit for Multiple Cycle ImplementationWhat are the control signals needed?Control Signals for Multicycle MIPSComplete Multi-cycle MIPSSlide 15Instruction fetch (PC increment)Slide 17Concept of “state”The first two statesCustomary notationTransitions from State 1State transitions from State 1State 2: Memory Address ComputationState 2: Memory address computationOne more example: State 5 --StoreMultiple Cycle ImplementationHardwired implementation of the control unitHardwired “diagram”01/14/19 CSE378 Multicycle impl,. 1Drawbacks of single cycle implementation•All instructions take the same time although–some instructions are longer than others; •e.g. load is longer than add since it has to access data memory in addition to all the other steps that add does–thus the “cycle” has to be for the “longest path”•Some combinational units must be replicated since used in the same cycle–e.g., ALU for computing branch address and ALU for computing branch outcome•but this is no big deal (these duplicate resources will be needed when we will pipeline instructions)01/14/19 CSE378 Multicycle impl,. 2Alternative to single cycle•Have a shorter cycle and instructions execute in multiple (shorter) cycles•The (shorter) cycle time determined by the longest delay in individual functional units (e.g., memory or ALU etc.)•Possibility to streamline some resources since they will be used at different cycles•Since there is need to keep information “between cycles”, we’ll need to add some stable storage (registers) not visible at the ISA level•Not all instructions will require the same number of cycles01/14/19 CSE378 Multicycle impl,. 3Multiple cycle implementation•Follows the decomposition of the steps for the execution of instructions–Cycle 1. Instruction fetch and increment PC–Cycle 2. Instruction decode and read source registers and branch address computation–Cycle 3. ALU execution or memory address calculation or set PC if branch successful–Cycle 4. Memory access (load/store) or write register (arith/log)–Cycle 5 Write register (load)•Note that branch takes 3 cycles, load takes 5 cycles, all others take 4 cycles01/14/19 CSE378 Multicycle impl,. 4Instruction fetch•Because fields in the instruction are needed at different cycles, the instruction has to be kept in stable storage, namely an Instruction Register (IR)•The register transfer level actions during this stepIR Memory[PC]PC PC + 4•Resources required–Memory (but no need to distinguish between instruction and data memories; later on we will because the need will reappear when we pipeline instructions)–Adder to increment PC–IR01/14/19 CSE378 Multicycle impl,. 5Instruction decode and read source registers•Instruction decode: send opcode to control unit and…(see later)•Perform “optimistic” computations that are not harmful–Read rs and rt and store them in non-ISA visible registers A and B that will be used as input to ALU A REG[IR[25:21]] (read rs)B REG[IR[20:16]] (read rt)–Compute the branch address just in case we had a branch!ALUout PC +(sign-ext(IR[15:0]) *4 (ALUout is also a non-ISA visible register)•New resources–A, B, ALUout01/14/19 CSE378 Multicycle impl,. 6ALU execution•If instruction is R-typeALUout A op. B•If instruction is Immediate ALUout A op. sign-extend(IR[15:0])•If instruction is Load/Store ALUout A + sign-extend(IR[15:0])•If instruction is branchIf (A=B) then PC ALUout (note this is the ALUout computed in the previous cycle)•No new resources01/14/19 CSE378 Multicycle impl,. 7Memory access or ALU completion•If LoadMDR Memory[ALUout] (MDR is the Memory Data Register non-ISA visible register)•If StoreMemory[ALUout] B•If arithReg[IR[15:11]] ALUout•New resources–MDR01/14/19 CSE378 Multicycle impl,. 8Load completion•Write result registerReg[IR[20:16]] MDR01/14/19 CSE378 Multicycle impl,. 9Streamlining of resources•No distinction between instruction and data memory•Only one ALU•But a few more muxes and registers (IR, MDR etc.)01/14/19 CSE378 Multicycle impl,. 10FloorPlan for Multicycle MIPS•01/14/19 CSE378 Multicycle impl,. 11Control Unit for Multiple Cycle Implementation•Control is more complex than in single cycle since:–Need to define control signals for each step–Need to know which step we are on•Two methods for designing the control unit–Finite state machine and hardwired control (extension of the single cycle implementation)–Microprogramming (read the book about it)01/14/19 CSE378 Multicycle impl,. 12What are the control signals needed? •Let’s look at control signals needed at each of 5 steps•Signals needed for–reading/writing memory–reading/writing registers–control the various muxes –control the ALU (recall how it was done for single cycle implementation)01/14/19 CSE378 Multicycle impl,. 13Control Signals for Multicycle MIPS•01/14/19 CSE378 Multicycle impl,. 14Complete Multi-cycle MIPS•01/14/19 CSE378 Multicycle impl,. 15Instruction fetch•Need to read memory –Choose input address (mux with signal IorD = 0)–Set MemRead signal–Set IRwrite signal (note that there is no write signal for MDR; Why?) •Set sources for ALU–Source 1: mux set to “come from PC” (signal ALUSrcA = 0)–Source 2: mux set to “constant 4” (signal ALUSrcB = 01)•Set ALU control to “+” (e.g., ALUop = 00 and don’t care for the function bits)01/14/19 CSE378 Multicycle impl,. 16Instruction fetch (PC increment)•Set the mux to store in PC as coming from ALU (signal PCsource = 01)•Set PCwrite–Note: this could be wrong if we had a branch but it will be overwritten in that case; see step 3 of branch instructions01/14/19 CSE378 Multicycle impl,. 17Instruction decode and read source registers•Read registers in A and B–No need for control signals. This will happen at every cycle. No problem since neither IR (giving names of the registers) nor the registers themselves are modified. When we need A and B as sources for the ALU, e.g., in step 3, the muxes will be set accordingly•Branch target computations. Select inputs for ALU–Source 1: mux set to “come
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