10/25/2005CSE378 Single cycleimplementation.1Levels in Processor Design•Circuit design–Keywords: transistors, wires etc.Results in gates, flip-flops etc.•Logical design–Putting gates (AND, NAND, …) and flip-flops together to build basic blocks such as registers, ALU’s etc (cf. CSE 370)•Register transfer –Describes execution of instructions by showing data flow between the basic blocks•Processor description (the ISA)•System description–Includes memory hierarchy, I/O, multiprocessing etc10/25/2005CSE378 Single cycleimplementation.2Register transfer level•Two types of components (cf. CSE 370)–Combinational : the output is a function of the input (e.g., adder)–Sequential: state is remembered (e.g., register)10/25/2005CSE378 Single cycleimplementation.3Synchronous design•Use of a periodic clock–edge-triggered clocking determines when signals can be read and when the output of circuits is stable–Values in storage elements can be updated only at clock edges–Clock tells when events can occur, e.g., when signals sent by control unit are obeyed in the ALUStorageElem 1Storage Elem 2Comb.logicClock cycleNote: the same storage element can be read/written in the same cycle10/25/2005CSE378 Single cycleimplementation.4Write signalWrite signalLogic may need several cycles to propagate valuesTrue in designs today with very high clock frequencyStorageElem 1Storage Elem 2Comb.logic10/25/2005CSE378 Single cycleimplementation.5Processor design: data path and control unitMemory hierarchyControl ALURegistersPCstateMemory busCPUData pathCombinationalSequential10/25/2005CSE378 Single cycleimplementation.6Processor design•Data path–How does data flow between various basic blocks–What operations can be performed when data flows–What can be done in one clock cycle•Control unit–Sends signals to data path elements–Tells what data to move, where to move it, what operations are to be performed•Memory hierarchy–Holds program and data10/25/2005CSE378 Single cycleimplementation.7Data path basic building blocks. Storage elements•Basic building block (at the RT level) is a register•In our mini-MIPS implementation registers will be 32-bits•A register can be read or writtenInput busOutput busWrite enable signalRegister10/25/2005CSE378 Single cycleimplementation.8Register file•Array of registers (32 for the integer registers in MIPS)•ISA tells us that we should be able to:–read 2 registers, write one register in a given instruction (at this point we want one instruction per cycle)–Register file needs to know which registers to read/writeWrite register numberWrite enableWrite data input busRead data output bus 0Read data output bus 1Read register number bus 0Read register number bus 1Register file10/25/2005CSE378 Single cycleimplementation.9Memory•Conceptually, like register file but much larger•Can only read one location or write to one location per cycleWrite enableWrite data busRead data bus Read control signalWrite memory addressRead memory addressMemory10/25/2005CSE378 Single cycleimplementation.10Combinational elementsMultiplexor (MUX): selects the value of one of its inputs to be routed to the outputInput bussesOutput busSelect control signalDemultiplexor (deMUX or SEL): routes its input to one of its outputsSelect control signalOutput bussesInput busMuxSel10/25/2005CSE378 Single cycleimplementation.11Arithmetic and Logic Unit (ALU - combinational)•Computes (arithmetic or logical operation) output from its two inputsALUInput bus 0Input bus 1Output busZero result bitALU control (opcode/function)10/25/2005CSE378 Single cycleimplementation.12Putting basic blocks together (skeleton of data path for arith/logical operations)Write register numberWrite enableWrite data input busRead data 0Read data 1Read register number bus 0Read register number bus 1Register fileZero result bitALU control (opcode/function)ALU10/25/2005CSE378 Single cycleimplementation.13Introducing instruction fetchRead data 0Read data 1Zero result bitALU control (opcode/function)Read Reg #0Read Reg #1Write Reg #Write dataReg. FileALUPCInstruction addressInstr. memory10/25/2005CSE378 Single cycleimplementation.14PC has to be incremented (assume no branch)PCInstruction addressInstr. memory4AdderInstruction10/25/2005CSE378 Single cycleimplementation.15Load-Store instructionsRead Reg #0Read Reg #1Write Reg #Reg. FileALUInstructionData from “load”Data memory16-bit offset32-bitSignextRead data 0“store” dataR/W addressRead enableWrite enable10/25/2005CSE378 Single cycleimplementation.16Load-Store instructionsRead Reg #0Read Reg #1Write Reg #Reg. FileALUInstructionData memory16-bit offset 32-bitSignextRead data 0“store” dataR/W addressRead enableWrite enableRead data 1Data for result registerMux10/25/2005CSE378 Single cycleimplementation.17Branch data pathPC4Inst. memoryAddrAddr32-bit16-bitSgn extSll
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