UW CSE 378 - Study Notes (16 pages)

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Study Notes



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Study Notes

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16
School:
University of Washington
Course:
Cse 378 - Machine Organization & Assembly Language
Machine Organization & Assembly Language Documents

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Pipeline Control unit highly abstracted Control Unit ID EX EX Mem Mem WB IF ID IF 01 14 19 ID EX Mem CSE378 Pipelining Control unit and hazards WB 1 Where are the control signals needed Very much like in multiple cycle implementation for the case of an ideal pipeline Cf Figure 6 25 01 14 19 CSE378 Pipelining Control unit and hazards 2 Control ideal case Control signals are split among the 5 stages For the ideal case no need for additional control but just wait Stage 1 nothing special to control read instr memory and increment PC asserted at each cycle Stage 2 nothing All instructions do the same Stage 3 Instruction dependent Control signals for ALU sources and ALUop Control signal for Regdest so the right name is passed along Stage 4 Control for memory read write and for branches Stage 5 Control for source of what to write in the destination register 01 14 19 CSE378 Pipelining Control unit and hazards 3 Hazards Recall structural hazards lack of resources won t happen in our simple pipeline data hazards due to dependencies between executing instructions control hazards flow of control is not sequential 01 14 19 CSE378 Pipelining Control unit and hazards 4 Data dependencies The result of an operation is needed before it is stored back in the register file Example add 7 12 15 put result in register 7 sub 8 7 12 use register 7 as a source and 9 14 7 use register 7 as a source The above dependence is called RAW Read After Write Note that there is no dependency for register 12 which is used as a source in two operations WAW Write After Write and WAR Write After Read dependencies can exist but not in our simple pipeline 01 14 19 CSE378 Pipelining Control unit and hazards 5 Data dependencies in the pipe Add 7 12 15 7 written here 7 needed here Sub 8 7 12 7 needed here And 9 14 7 01 14 19 CSE378 Pipelining Control unit and hazards 6 Occurrences of data dependencies detection Data dependence RAW occurs when An instruction wants to read a register in stage 2 and One



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