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UW CSE 378 - Lecture Notes

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110/22/2004 CSE378 Control unitSingle cycle impl.1Control Unit (single cycleimplementation)• Control unit sends control signals to data path and memory depending– on the opcode (and function field)– results in the ALU (for example for Zero test)• These signals control– muxes; read/write enable for registers and memory etc.• Some “control” comes directly from instruction– register names• Some actions are performed at every instruction so no need for control (in this single cycle implementation)– incrementing PC by 4; reading instr. memory for fetching next inst.10/22/2004 CSE378 Control unitSingle cycle impl.2Building the control unit• Decompose the problem into– Data path control (register transfers)– ALU control• Setting of control lines by control unit totally specified in the ISA– for ALU by opcode + function bits if R-R format– for register names by instruction (including opcode)– for reading/writing memory and writing register by opcode– muxes by opcode– PC by opcode + result of ALU10/22/2004 CSE378 Control unitSingle cycle impl.3Example• Limit ourselves to:– R-R instructions: add, sub, and, or, slt –• OPcode = 0 but different function bits– Load-store: lw, sw– Branch: beq• ALU control– Need to add for: add, lw, sw– Need to sub for: sub, beq– Need to and for :and– Need to or for :or– Need to set less than for : slt10/22/2004 CSE378 Control unitSingle cycle impl.4ALU Control• ALU control: combination of opcode and function bits• Decoding of opcodes yields 3 possibilities hence 2 bits– AluOp1 and ALUOp2• ALU control:– Input 2 ALUop bits and 6 function bits– Output one of 5 possible ALU functions– Of course, lots of don’t care for this *very* limited implementation10/22/2004 CSE378 Control unitSingle cycle impl.5Implementation of Overall Control Unit• Input: opcode (and function bits for R-R instructions)• Output: setting of control lines• Can be done by logic equations• If not too many, like in RISC machines– Use of PAL’s (cf. CSE 370).– In RISC machines the control is “hardwired”• If too large (too many states etc.)– Use of microprogramming (a microprogram is a hardwired program that interprets the ISA)• Or use a combination of both techniques (Pentium)10/22/2004 CSE378 Control unitSingle cycle impl.6Where are control signals needed (cf. Figure 5.13)• Register file– RegWrite (Register write signal for R-type, Load)– RegDst (Register destination signal: rd for R-type, rt for Load)• ALU– ALUSrc (What kind of second operand: register or immediate)– ALUop (What kind of function: ALU control for R-type)• Data memory– MemRead (Load) or MemWrite (Store)– MemtoReg (Result register written from ALU or memory)• Branch control– PCSrc (PC modification if branch is taken)210/22/2004 CSE378 Control unitSingle cycle impl.7MIPS FloorPlan & Control lines10/22/2004 CSE378 Control unitSingle cycle impl.8Basic 3 Operation 1-bit ALU10/22/2004 CSE378 Control unitSingle cycle impl.9Chain Together 32 “3 Op 1-bit ALUs”10/22/2004 CSE378 Control unitSingle cycle impl.10Basic 4 Operation 1-bit ALU10/22/2004 CSE378 Control unitSingle cycle impl.11Adding SLT to 1-bit ALU & Detect Overflow10/22/2004 CSE378 Control unitSingle cycle impl.12Chain Together 32 “1-bit ALUs”310/22/2004 CSE378 Control unitSingle cycle impl.13ALU floorplan & Symbol10/22/2004 CSE378 Control unitSingle cycle impl.14Control lines10/22/2004 CSE378 Control unitSingle cycle impl.15How are the control signals asserted • Decoding of the opcode by control unit yields– Control of the 3 muxes (RegDst, ALUSrc,MemtoReg): 3 control lines– Signals for RegWrite, Memread,Memwrite: 3 control lines– Signals to activate ALU control (e.g., restrict ourselves to 2)– Signal for branch (1 control line)• decoding of opcode ANDed with ALU zero result• Input Opcode: 6 bits• Output 9 control lines10/22/2004 CSE378 Control unitSingle cycle impl.16Control linesSignal R-typelw sw beqRegDest 1 0 X XALUSrc 0 1 1 0MemtoReg 0 1 X XRegWrite 1 1 0 0MemRead 0 1 0 0MemWrite 0 0 1 0Branch 0 0 0 1ALUOp1 1 0 0 0ALUOp0 0 0 0 110/22/2004 CSE378 Control unitSingle cycle impl.17Signal R-typelw sw beqOp5 0 1 1 0Op4 0 0 0 0Op3 0 0 1 0Op2 0 0 0 1Op1 0 1 1 0Op0 0 1 1 0RegDest 1 0 X XALUSrc 0 1 1 0MemtoReg 0 1 X XRegWrite 1 1 0 0MemRead 0 1 0 0MemWrite 0 0 1 0Branch 0 0 0 1ALUOp1 1 0 0 0ALUOp0 0 0 0 1ORANDOp5Op4Op3Op2Op1Op0AND AND ANDRegDstALUSrcMemtoRegRegWriteMemReadMemWriteBranchALUOp1ALUOp0ORComputing the Control10/22/2004 CSE378 Control unitSingle cycle impl.18Suppose the following times apply ...Memory units: 10nsALU and adders: 10nsRegister file ref: 5nsAll other operations are 0ns.Charges for instructions are ...R-format: 30nsLoad inst: 40nsStore inst: 35nsBranch: 25nsJump: 10nsInstruction Mix GCC22% Load11% Store49% R-type16% Branch2% JumpComputing the Cycle


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