requirements document forDesign of a Lateral MOSFET in Silicon Carbidesubmitted to:Professor Joseph PiconeECE 4522: Senior Design IIDepartment of Electrical and Computer EngineeringMississippi State UniversityMississippi State, Mississippi 39762August 21, 2000submitted by:Janna Bonds Dufrene, Chris Sanders, Elmer Durrell, Wendy EvansFaculty Advisor: Dr. Jeffrey CasadyDepartment of Electrical and Computer EngineeringMississippi State UniversityBox 9571Mississippi State, Mississippi 39762Tel: 662-325-3912, Fax: 662-325-2298email: { jrb2@ece, crs4@ra, ed1@ece, wle1@ra }.msstate.eduDesign of a Lateral MOSFET in Silicon CarbideDesign of a Lateral MOSFET in Silicon CarbideEXECUTIVE SUMMARYDue to silicon carbide’s high breakdown strength and high thermal conductivity [1], it is anideal semiconductor material for the implementation of devices used in high power switchingand high power microwave applications. Devices used in these applications require a highinversion layer electron mobility, low on-resistance and high breakdown voltage. Because ofmaterial characteristics and designs, it is hard to obtain high breakdown voltage devices withextremely low on-resistances and high inversion layer mobility. Implementation of newtechniques to improve material processes and design of these devices, is expected to result in ahigher breakdown voltage, a lower on-resistance and a greater electron mobility. Several design constraints must be used in order to design a device which will contain theoptimal characteristics for both high power and high speed switching applications. A 10 m p-type epitaxy, with a dopant concentration in the range of 5e15 cm-3 to 1e16 cm-3, is to be grown,via chemical vapor deposition on a heavily doped p-type 6H-SiC wafer. The device will have anoptimal gate width and gate length between 100 m to 1 mm and 3 m to 10 m, respectively,and have an active area no larger than 500 m by 500 m . The contact resistance should notexceed 1 mOhms-cm². An ion implantation will be done on the n+ drain and source regions toachieve a doping concentration near 1e20 cm-3. The n-type drift region will be a layer ofepitaxy with a doping concentration around 5e16 cm-3 to 1e17 cm-3 and will vary in lengthbetween 6 m to 18 m [2].After researching existing lateral SiC MOSFET designs, various simulation tools will be used tostudy the effects of varying doping concentration, channel length and drift length. Afterachieving desired results, the process design will be developed and masks required forfabrication will be created using Cadence tools. The feasibility of the mask design will then bereviewed by the project manager and SiC fabrication foundry (General Electric Corporation). Ifno discrepancies are found, then the masks will be produced. The MOSFET will be fabricatedusing the full wafer epitaxy that has been grown at EMRL (Emerging Materials and ResearchLaboratory) using the developed controlled p-type dopant method. Quality epitaxy will be grown to help control breakdown in the lateral silicon carbide MOSFET.This will be possible by developing improvements to control p-type dopant in silicon carbide.Additionally, by implementing a tube reactor capable of handling a wafer up to 75 mm indiameter, manufacturing costs will be lowered. To help with mobility in the device, an implantanneal process developed by EMRL [1] will be used. It will result in a smoother silicon carbidesurface and a fully activated aluminum or boron p-type implant without causing major step-bunching. The success of this design will impact power applications in the areas related to hightemperature and high voltage. Silicon carbide devices could then replace silicon devices inECE 4522 August 21, 2000Design of a Lateral MOSFET in Silicon Carbidethese power applications, eliminating a large fraction of the required passive elements [2],reducing size and possibly cost. Success in this area will provide for improvement in numerousmilitary applications as well as consumer applications. This design will be improved in thefuture due to expanding technologies that will decrease gate lengths and lead to new dopingmethods. ECE 4522 August 21, 2000Design of A Lateral MOSFET in Silicon Carbide Page 1 of51. PROBLEMWith technology increasing on a geometric level, it is expected that MOSFET devices becomeless costly, more efficient, higher powered and smaller in size. The most widely usedsemiconductor, silicon, is approaching the limits of its capabilities; therefore, an improvedsemiconductor is needed to advance technologies further. High power switching and high powermicrowave applications require devices with higher breakdown strength and greater thermalconductivity [3]. Silicon carbide offers the characteristics needed to advance these applications.These characteristics include a breakdown voltage ten times better, an on-resistance 300 timeslower [4], and a switching capability faster than that of silicon. Due to lack of materialdevelopment and design, devices with high blocking voltages have not possessed predictedminimum on-resistance values.Annealing processes result in surface problems such as step-bunching, non-uniform dopingdensity and non-uniform epitaxy layer thickness. This leads to poor inversion layer electronmobility and oxide reliability, which reduce breakdown voltage and switching speed capabilities.An alternate annealing process method, such as silane over-pressure, is necessary to minimizethis problem. The ability to have controlled p-type doping in SiC epitaxy systems across largediameter wafers also reduces non-uniformity problems with doping density and epitaxy layerthickness. When processes that allow for uniform doping density, uniform epitaxy layerthickness and smooth silicon carbide surfaces are utilized, then higher performance devices willbe obtainable.Higher breakdown voltages provide for improvements in high power device performance, but thisconflicts with the need for high switching devices to have a low on-resistance [3]. Thebreakdown
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