test certification forDesign of a Lateral MOSFET in Silicon Carbidesubmitted to:Professor Joseph PiconeECE 4522: Senior Design IIDepartment of Electrical and Computer EngineeringMississippi State UniversityMississippi State, Mississippi 39762August 21, 2000submitted by:Janna Bonds Dufrene, Chris Sanders, Elmer Durrell, Wendy EvansFaculty Advisor: Dr. Jeffrey CasadyDepartment of Electrical and Computer EngineeringMississippi State UniversityBox 9571Mississippi State, Mississippi 39762Tel: 662-325-3912, Fax: 662-325-2298email: { jrb2@ece, crs4@ra, ed1@ece, wle1@ra }.msstate.eduDesign of a Lateral MOSFET in Silicon CarbideECE 4522 August 21, 2000EXECUTIVE SUMMARYDue to silicon carbide’s high breakdown strength and high thermal conductivity [1], it is an idealsemiconductor material for the implementation of devices used in high power switching and highpower microwave applications. Devices used in these applications require a high inversion layerelectron mobility, low on-resistance and high breakdown voltage. Because of materialcharacteristics and designs, it is hard to obtain high breakdown voltage devices with extremelylow on-resistances and high inversion layer mobility. Implementation of new techniques toimprove material processes and design of these devices, is expected to result in a higherbreakdown voltage, a lower on-resistance and a greater electron mobility.Several design constraints must be used in order to design a device which will contain theoptimal characteristics for both high power and high speed switching applications. A 10 µm p-type epitaxy, with a dopant concentration in the range of 5e15 cm-3 to 1e16 cm-3, is to be grown,via chemical vapor deposition on a heavily doped p-type 6H-SiC wafer. The device will have anoptimal gate width and gate length between 100 µm to 1 mm and 3 µm to 10 µm, respectively,and have an active area no larger than 500 µm by 500 µm . The contact resistance should notexceed 1 mΩ-cm². An ion implantation will be done on the n+ drain and source regions toachieve a doping concentration near 1e20 cm-3. The n-type drift region will be a layer of epitaxywith a doping concentration around 5e16 cm-3 to 1e17 cm-3 and will vary in length between 6 µmto 18 µm [2].After researching existing lateral SiC MOSFET designs, various simulation tools will be used tostudy the effects of varying doping concentration, channel length and drift length. Afterachieving desired results, the process design will be developed and masks required forfabrication will be created using Cadence tools. The feasibility of the mask design will then bereviewed by the project manager and SiC fabrication foundry (General Electric Corporation). Ifno discrepancies are found, then the masks will be produced. The MOSFET will be fabricatedusing the full wafer epitaxy that has been grown at EMRL (Emerging Materials and ResearchLaboratory) using the developed controlled p-type dopant method.Quality epitaxy will be grown to help control breakdown in the lateral silicon carbide MOSFET.This will be possible by developing improvements to control p-type dopant in silicon carbide.Additionally, by implementing a tube reactor capable of handling a wafer up to 75 mm indiameter, manufacturing costs will be lowered. To help with mobility in the device, an implantanneal process developed by EMRL [1] will be used. It will result in a smoother silicon carbidesurface and a fully activated aluminum or boron p-type implant without causing major step-bunching.The success of this design will impact power applications in the areas related to high temperatureand high voltage. Silicon carbide devices could then replace silicon devices in these powerapplications, eliminating a large fraction of the required passive elements [2], reducing size andpossibly cost. Success in this area will provide for improvement in numerous militaryapplications as well as consumer applications. This design will be improved in the future due toexpanding technologies that will decrease gate lengths and lead to new doping methods.Design of A Lateral MOSFET in Silicon Carbide Page 1 of 44ECE 4522 August 21,20001. INTRODUCTIONDue to the fact that silicon has reached its theoretical limits, silicon carbide is being researchedfor processes and designs that will result in devices, such as power MOSFETs, that surpasssilicon technology. The objective is to design a small active area device with low on-resistanceand contact resistance capable of blocking high voltages. By using new epitaxial growthmethods, device layout designs and fabrication processes, a lateral silicon carbide MOSFETdesign will be created to achieve these objectives. This device will serve as a model for futurelateral silicon carbide MOSFET designs that will improve private applications as well asconsumer applications in power electronics. Below are design constraints for the project:1. Epi Growth: Develop and design a repeatable process to grow p-type epitaxy with thedopant concentration between the range of 5e15 cm-3 to 1e16 cm-3.2. Fabrication Process: Complete process traveler for the MOSFET fabrication sequenceto be executed by the SiC fabrication foundry.3. Device Layout: Layout masks used for fabrication of the MOSFETs using Cadencetools, following closely the outlined design constraints.4. Blocking Voltage: Devices will be designed to achieve blocking voltages of 600 V,1200 V and 1800 V.5. On-Resistance: Devices will be designed to have on-resistances of 50 mΩ-cm2, 350mΩ-cm2 and 2450 mΩ-cm2 , for 600 V, 1200 V and 1800 V, respectively.6. Contact Resistance: The contact resistance will be around 1 mΩ-cm2 to minimize theseries resistance affect.7. Physical Size: The total active area of the device will be no larger than 500 µm x 500µm.8. Cost: The estimated cost to produce and manufacture the set of masks will be around$4,000, and 4 wafers with epi layer will cost approximately $6,000.Using these design constraints, a suitable MOSFET design should be acquired that will result inachieving the desired objectives.Medici and Cadence have served as important simulation tools in the field of
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