Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface GeneratorMemory Interface Trends and Xilinx SolutionsLow-Cost Memory InterfacesHigh-Performance Memory InterfacesController Design and IntegrationHigh-Performance System DesignDevelopment Boards for Memory InterfacesConclusionRevision HistoryWP260 (v1.0) February 16, 2007 www.xilinx.com 1© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All othertrademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you mayrequire for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warrantiesor representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. As FPGA designers strive to achieve higherperformance while meeting critical timing margins,the memory interface design is a consistentlydifficult and time-consuming challenge. XilinxFPGAs provide I/O blocks and logic resources thatmake the interface design easier and more reliable.Nonetheless, the I/O blocks, along with extra logic,must be configured, verified, implemented andproperly connected to the rest of the FPGA by thedesigner in the source RTL code, carefully simulated,and then verified in hardware to ensure a reliablememory interface system.This white paper discusses the various memoryinterface controller design challenges and Xilinxsolutions. It also describes how to use the Xilinxsoftware tools and hardware-verified referencedesigns to build a complete memory interfacesolution for your own application, from low-costDDR SDRAM applications to higher-performanceinterfaces like the 667 Mb/s DDR2 SDRAMs.White Paper: Virtex-4, Virtex-5, and Spartan-3 Generation FPGAsWP260 (v1.0) February 16, 2007Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface GeneratorBy: Adrian CosoroabaR2 www.xilinx.com WP260 (v1.0) February 16, 2007Memory Interface Trends and Xilinx SolutionsRMemory Interface Trends and Xilinx SolutionsIn the late 1990s, memory interfaces evolved from single-data-rate (SDR) SDRAMs to double-data-rate (DDR) SDRAMs, with today's DDR2 SDRAMs running at 667 Mb/s per pin or higher. Present trends indicate that these rates are likely to double every four years, potentially reaching over 1.2 Gb/s per pin by the year 2010 with the upcoming DDR3 SDRAMs. See Figure 1.Applications can generally be classified in two categories: low-cost applications, where the cost of the device is most important; and high-performance applications, where getting the highest bandwidth is paramount. DDR SDRAMs and low-end DDR2 SDRAMs running below 400 Mb/s per pin are adequate to meet most low-cost systems memory bandwidth requirements. For these applications, Xilinx offers the Spartan™-3 Generation FPGAs: Spartan-3, Spartan-3E, and Spartan-3A devices. For high-performance applications, pushing the limits of the memory interface bandwidth like 533 and 667 Mb/s per pin DDR2 SDRAMs, Xilinx offers the Virtex™-4 and Virtex-5 FPGAs, which are capable of meeting the highest bandwidth requirements of most systems today. Bandwidth is a factor related to both the data rates per pin and the width of the data bus. Spartan-3 Generation, Virtex-4, and Virtex-5 FPGAs offer distinct options that span from smaller low-cost systems, with data bus widths of less than 72 bits, to 576 bits wide for the larger Virtex-5 packages (see Figure 2).Figure 1: DRAM Data Rates Trends and Xilinx FPGA SolutionsYear1998 2002 2006040080012001600SDRAMData Rate per Pin (Mb/s)DDRDDR2DDR3667WP260_01_011007Spartan-3 Generation FPGAsLow Cost ApplicationsVirtex-4 and Virtex-5 FPGAsHigh Performance ApplicationsLow-Cost Memory InterfacesWP260 (v1.0) February 16, 2007 www.xilinx.com 3RWider buses at more than 400 Mb/s make the chip-to-chip interfaces all the more challenging. Larger packages and better power- and ground-to-signal ratios are required. Virtex-4 and Virtex-5 FPGAs have been built with advanced Sparse Chevron packaging, which provides superior signal-to-power and ground-pin ratios. Every I/O pin is surrounded by sufficient power and ground pins and planes to ensure proper shielding for minimum crosstalk noise caused by simultaneously switching outputs (SSO).Low-Cost Memory InterfacesNot all systems built today push the performance limits for memory interfaces. When low cost is a primary decision driver and memory bit rates per pin of up to 333 Mb/s are sufficient, the Spartan-3 Generation of FPGAs coupled with Xilinx software tools provide an easy-to-implement, low-cost solution.A memory interface and controller for an FPGA-based design have three fundamental building blocks: the Read and Write Data interface, the memory controller state machine, and the user interface that bridges the memory interface design to the rest of the FPGA design (Figure 3). These blocks, implemented in the fabric, are clocked by the output of the Digital Clock Manager (DCM). In the Spartan-3 Generation implementation, the DCM also drives the Look-Up Table (LUT) delay calibration monitor (a block of logic that ensures proper timing for Read Data capture). The delay calibration circuit is used to select the number of LUT-based delay elements used to delay the strobe lines (DQS) with respect to Read Data. The delay calibration circuit calculates the delay of a circuit that is identical in all respects to the strobe delay circuit. Figure 2: Xilinx FPGAs and Memory Interfaces BandwidthData Bus Width (I/Os)144720432288 5760200400333600667Data Rate per Pin (Mb/s)WP260_02_020507Spartan-3GenerationFPGAsVirtex-5 FPGAs4 www.xilinx.com WP260 (v1.0) February 16, 2007Low-Cost Memory InterfacesRAll aspects of the delay are considered for calibration, including all the component and route delays. The user interface is a handshaking-type interface. The user sends a command, Read or Write,