1 Veriolog Overview CS/EE 3710 Fall 2010 Hardware Description Languages  HDL  Designed to be an alternative to schematics for describing hardware systems  Two main survivors  VHDL  Commissioned by DOD  Based on ADA syntax  Verilog  Designed by a company for their own use  Based on C syntax2 Verilog Origins  Developed as a proprietary HDL by Gateway Design Automation in 1984  Acquired by Cadence in 1989  Made an open standard in 1990  Made an IEEE standard in 1995  IEEE standard Revised in 2001 Verilog  You can think of it as a programming langauge  BUT, that can get you into trouble!  Better to think of is as a way to describe hardware  Begin the design process on paper  Plan the hardware you want  Use Verilog to describe that hardware3 Quick Review Module name (args…); begin parameter ...; // define parameters input …; // define inputs output …; // define outputs wire … ; // internal wires reg …; // internal regs, possibly output // the parts of the module body are // executed concurrently <continuous assignments> <always blocks> endmodule Quick Review (2001 syntax) Module name (parameters, inputs, outputs); begin wire … ; // internal wires reg …; // internal regs // the parts of the module body are // executed concurrently <continuous assignments> <always blocks> endmodule4 Quick Review  Continuous assignments to wire vars  assign variable = exp;  Results in combinational logic  Procedural assignment to reg vars  Always inside procedural blocks (always blocks in particular for synthesis)  blocking  variable = exp;  non-blocking  variable <= exp;  Can result in combinational or sequential logic Verilog Description Styles  Verilog supports a variety of description styles  Structural  explicit structure of the circuit  e.g., each logic gate instantiated and connected to others  Hierarchical instantiations of other modules  Behavioral  program describes input/output behavior of circuit  many structural implementations could have same behavior  e.g., different implementation of one Boolean function5 Synthesis: Data Types  Possible Values (wire and reg):  0: logic 0, false  1: logic 1, true  Z: High impedance  Digital Hardware  The domain of Verilog  Either logic (gates)  Or storage (registers & latches)  Verilog has two relevant data types  wire  reg Synthesis: Data Types  Register declarations  reg a; \\ a scalar register  reg [3:0] b; \\ a 4-bit vector register  output g; \\ an output can be a reg reg g;  output reg g; \\ Verilog 2001 syntax  Wire declarations  wire d; \\ a scalar wire  wire [3:0] e; \\ a 4-bit vector wire  output f; \\ an output can be a wire6 Number Syntax  Numbers with no qualifiers are considered decimal  1 23 456 etc.  Can also qualify with number of digits and number base  base can be b, B, h, H, d, D, o, O 4'b1011 // 4-bit binary of value 1011 234 // 3-digit decimal of value 234 2'h5a // 2-digit (8-bit) hexadecimal of value 5A 3'o671 // 3-digit (9-bit) octal of value 671 4b'1x0z // 4-bit binary. 2nd MSB is unknown. LSB is Hi-Z. 3.14 // Floating point 1.28e5 // Scientific notation Parameters  Used to define constants  parameter size = 16, foo = 8;  wire [size-1:0] bus; \\ defines a 15:0 bus7 Synthesis: Assign Statement  The assign statement creates combinational logic  assign LHS = expression;  LHS can only be wire type  expression can contain either wire or reg type mixed with operators  wire a, c; reg b; output out; assign a = b & c; assign out = ~(a & b); \\ output as wire  wire [15:0] sum, a, b; wire cin, cout; assign {cout,sum} = a + b + cin; Synthesis: Basic Operators  Bit-Wise Logical  ~ (not), & (and), | (or), ^ (xor), ^~ or ~^ (xnor)  Simple Arithmetic Operators  Binary: +, -  Unary: -  Negative numbers stored as 2’s complement  Relational Operators  <, >, <=, >=, ==, !=  Logical Operators  ! (not), && (and), || (or) assign a = (b > ‘b0110) && (c <= 4’d5); assign a = (b > ‘b0110) && !(c > 4’d5);8 Synthesis: More Operators  Concatenation  {a,b} {4{a==b}} { a,b,4’b1001,{4{a==b}} }  Shift (logical shift)  << left shift  >> right shift assign a = b >> 2; // shift right 2, division by 4 assign a = b << 1; // shift left 1, multiply by 2  Arithmetic assign a = b * c; // multiply b times c assign a = b * ‘d2; // multiply b times constant (=2) assign a = b / ‘b10; // divide by 2 (constant only) assign a = b % ‘h3; // b modulo 3 (constant only) Synthesis: Operand Length  When operands are of unequal bit length, the shorter operator is zero-filled in the most significant bit position wire [3:0] sum, a, b; wire cin, cout, d, e, f, g; assign sum = f & a; assign sum = f | a; assign sum = {d, e, f, g} & a; assign sum = {4{f}} | b; assign sum = {4{f == g}} & (a + b); assign sum[0] = g & a[2]; assign sum[2:0] = {3{g}} & a[3:1];9 Synthesis: Operand Length  Operator length is set to the longest member (both RHS & LHS are considered). Be careful. wire [3:0] sum, a, b; wire cin, cout, d, e, f, g; wire[4:0]sum1; assign {cout,sum} = a + b + cin; assign {cout,sum} = a + b + {4’b0,cin}; assign sum1 = a + b; assign sum = (a + b) >> 1; // what is wrong? Synthesis: Extra Operators  Funky Conditional  cond_exp ? true_expr : false_expr wire [3:0] a,b,c; wire d, sel; assign a = d ? b : c; // Mux with d as select assign a = (b == c) ? (c + ‘d1): ‘o5; // good luck  Reduction Logical  Named for impact on your recreational time  Unary operators that perform bit-wise operations on a single operand, reduce it to one bit  &, ~&, |, ~|, ^, ~^, ^~ assign d = &a || ~^b ^ ^~c;10 Synthesis: Assign Statement  The assign statement is sufficient to create all combinational logic  What about this: assign a = ~(b & c); assign c = ~(d & a);