1CS/EE 3710National Semiconductor CR16 Compact RISC ProcessorBaseline ISA and Beyond… University of UtahCS/EE 3710CR16 Architecture Part of a microcontroller family from National Semiconductor 16-bit embedded RISC processor core Available in Synethesizeable Verilog HDL Die size of 0.6 mm2 @ 0.25µ 2 Mbytes of linear address space Less than 0.2mA per MHZ @ 3 Volts, 0.35µ This has morphed into the CP3000 family...2University of UtahCS/EE 3710CR16 Architecture More specs… Static 0 to 66 MHz clock frequency Atomic memory-direct bit manipulation instructions Save and Restore of Multiple Registers Push and Pop of Multiple Registers Hardware Multiplier Unit for fast 16-bit multiplicationUniversity of UtahCS/EE 3710CR16 Block Diagram3University of UtahCS/EE 3710CR16 Register Set All registers are 16 bits wide Except address registers which are 21 bits Original version used 18 bits… 16 general purpose registers 8 processor registers 3 dedicated address registers (PC, ISP, INTBASE) 1 Processor Status Register 1 configutation register 3 debug-control registersUniversity of UtahCS/EE 3710CR16 Registers4University of UtahCS/EE 3710Processor Registers PSR – Processor Status Register C, T, L, F, Z, N, E, P, I bits Carries, conditions, interrupt enables, etc. INTBASE - Interrupt Base register Holds the address of the dispatch table for interrupts and traps ISP – Interrupt Stack Pointer Points to the lowest address of the last item stored on the interrupt stackUniversity of UtahCS/EE 3710CR16 Instruction Encoding More complex than our version…5University of UtahCS/EE 3710CR16 Instructions Most ALU instructions have two forms MOVi -> MOVW or MOVB Two-address instruction formal One of the two arguments is also used as destination (Rdest) and is overwritten ADD R0, R3 => R3 := R0 + R3 Little-Endian data references Least-significant is lowest numbered Both bits and bytesUniversity of UtahCS/EE 3710CR16 Instructions6University of UtahCS/EE 3710More CR16 InstructionsUniversity of UtahCS/EE 3710Even More CR16 Instructions7University of UtahCS/EE 3710Still More CR16 InstructionsUniversity of UtahCS/EE 3710More and More Instructions8University of UtahCS/EE 3710CR16 Memory MapUniversity of UtahCS/EE 3710CR16 Exceptions Interrupt Exception caused by external activity CR16 recognizes three types, Maskable, Non-maskable, and ISE (In-System Emulator) Trap Exception caused by program action Six types: SVC, DVZ, FLG, BPT, TRC, UND Interrupt process saves PC and PSR on interrupt stack, RETX returns from interrupt9University of UtahCS/EE 3710CR16 Pipeline Three stage pipe Fetch Decode Execute Instruction execution is serialized after an exception Also serialized after LPR, RETX, and EXCPUniversity of UtahCS/EE 3710Our Class Version! Baseline instruction set uses (almost) fixed instruction encoding Detailed description on the web page All instructions are a single 16-bit word All memory references (inst or data) operate on 16-bit words Not all instructions are included Each group will extend the baseline ISA somehow10University of UtahCS/EE 3710Baseline ISA ADD, ADDI, SUB, SUBI CMP, CMPI AND, ANDI, OR, ORI, XOR, XORI MOV, MOVI LSH, LSHI (restricted to shift of one) LUI, LOAD, STOR Bcond, Jcond, JALUniversity of UtahCS/EE 3710Class Encoding In the handout on the web Much more regular than real CR1611University of UtahCS/EE 3710Data Types All data is 16-bit Two’s complement encoding for data Unsigned for address manipulation Boolean for boolean operations Of course, the ALU doesn’t know which is which – they’re all 16bit clumps to the ALU! Flags are set for all interpretationsz The programmer can sort out the flags laterUniversity of UtahCS/EE 3710PSR Issues Only ADD, ADDI, SUB, SUBI, CMP, CMPIcan change the PSR flags CMP, CMPI are the same as SUB, SUBI But, they affect the PSR differently Only PSR bits FLCNZ are needed for baseline implementation ADD, ADDI, SUB, SUBI set the C on carry out and F on overflow CMP, CMPI set Z, L (unsigned), and N (signed)12University of UtahCS/EE 3710Conditional Jumps/Branches Jumps are absolute Branches are relative to current PC JAL Jump and Link stores the address of the next instruction in Rlink, and jumps to Rtarget Return with JUC Rlink Conditions are derived from PSR bitsUniversity of UtahCS/EE 3710Condition Table13University of UtahCS/EE 3710Memory Map 16 bit PC and LOAD/STOR addresses 64k addresses Each address is a 16-bit word So, 128k bytes of data, but organized as wordsz But, only 40k bytes of block RAM on Spartan-3Ez But, 64M bytes of SDRAMz But, SRDAM is a pain... We need to reserve some I/O addressesz Up to you, but I recommend using the some top address bitsz Upper 16k words (32kbytes) as I/O space?University of UtahCS/EE 3710Memory MapI/OSwitches/LEDsUARTCode/DataCode/DataCode/Data00003FFF40007FFF8000BFFFC000FFFF16k words32k bytesTop two addressbits define regionsInterrupt dispatchtables?
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