Creating High-Speed Memory Interfaces with Virtex-II and Virtex-II Pro FPGAsSummaryIntroductionKey ChallengesPhysical LayerClocks, Address and Control SignalsData WriteStrobe Delay CircuitData ReadData CaptureData RecaptureDelay Calibration CircuitControl Layer and Application Interface LayerToolsImplementationBoard Design ConsiderationsDDR-1 SDRAM InterfaceQDR-2 SRAM InterfaceRLDRAM-2/FCRAM-2 InterfacesReferencesConclusionRevision HistoryXAPP688 (v1.2) May 3, 2004 www.xilinx.com 11-800-255-7778© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.Summary Designing high-speed memory interfaces is a challenging task. Xilinx has invested time and effort to make it simple to design such interfaces using the Virtex-II™ and Virtex-II Pro™ FPGAs. This application note discusses the challenges presented by this task together with various techniques that can be used to overcome them, while illustrating the key concepts in implementing any memory interface. All examples used in this application note assume a DDR-1 interface on an XC2VP20FF1152-6 Virtex-II Pro FPGA. The interface speed is 200 MHz.Introduction High-speed memory interfaces are typically source-synchronous and double-data rate. In a source-synchronous design, the clocks are generated and transmitted along with the data, as shown in Figure 1. The data is typically received using the received clock and then transferred into the receivers' clock domain. A memory interface can be modularly represented as shown in Figure 2. Creating a modular interface has many advantages. It allows designs to be ported easily. It also makes it possible to share parts of the design across different types of memory interfaces. Application Note: Virtex-II FamiliesXAPP688 (v1.2) May 3, 2004Creating High-Speed Memory Interfaces with Virtex-II and Virtex-II Pro FPGAsAuthor: Nagesh Gupta, Maria GeorgeRFigure 1: Source Synchronous Memory InterfaceXilinx FPGAData Sources Data SinkRead ClockRead DataRead ClockRead DataRead ClockRead Datax688_01_0904032 www.xilinx.com XAPP688 (v1.2) May 3, 20041-800-255-7778Key ChallengesRKey Challenges High-speed controllers and interfaces are challenging to design. Designing high-speed memory interfaces are particularly challenging due to various factors. Some of the key challenges are • Source-synchronous data transmit (data write function). • Source-synchronous data receive (data read function).While these functions are common in all high-speed interfaces, memory interfaces make it particularly challenging due to the following factors:•Single-ended standards. Memories typically use HSTL or SSTL type input/output standard.• Non-free-running clocks. Some memories such as DDR SDRAM provide a non free-running strobe clock for data reads.• Timing parameters. The input and output timing specifications for memories take away significant amount of the available data valid window. We have solved these key problems with patent-pending innovations. These innovations have been proven in hardware and are available for use in the form of reference designs.Physical Layer The Physical layer is responsible for transmitting and receiving all the signals to and from the memories. The major functions of the physical layer include:• Write data into the memory.• Read data from the memory.• Provide all the necessary control signals• Transfer the read data clock domain from memory domain to FPGA domain.The physical layer constitutes a major challenge in memory interface design. This section elaborates on the different aspects of the physical layer.Figure 2: Modular Memory Interface Representationx688_02_090403Xilinx FPGAArbitration LayerControl LayerPhysical LayerApplication Interface LayerMemoriesPhysical LayerXAPP688 (v1.2) May 3, 2004 www.xilinx.com 31-800-255-7778RClocks, Address and Control SignalsThe FPGA generates all the clocks and control signals for reads and writes to memory. The memory clocks are typically generated using a Double Data Rate (DDR) register. As shown in Figure 3, a Digital Clock Manger (DCM) generates the clock and its inverted version. Generating the clock this way has a couple advantages: • The data, control and clock signals all go through similar delay elements while exiting the FPGA. • Clock duty cycle distortion is minimal when global clock nets are used for the clock and the 180° phase-shifted clock.All of the address and control signals are registered and output at the IOB. The address and control signals are registered using a clock that is 180° shifted from the clock signal to the memory. Such an approach enables the address and control signals to have additional time margin before they are registered. The address and control signals meet the required timing with ease. An example timing analysis for a DDR-1 interface implemented using an XC2VP20FF1152 FPGA, -6 speed grade, is shown inTable 1 . Figure 3: Clock Generation for Memory DeviceClock0BUFGVCCBUFGDCMClock180IOBClock toMemoryController&TransmitData Pathx688_03_090803Table 1 : Address and Control Signal MarginsParameter ValueLeading-Edge UncertaintiesTrailing-Edge UncertaintiesMeaningTCLOCK5000 Clock periodTCLOCK_SKEW50 50 50Minimal skew, since right/left sides are being used and the bits are close togetherTPACKAGE_SKEW65 65 65 Using same bank reduces package skewTSETUP750 750 0 Setup time from memory data sheetTHOLD750 0 750 Hold time from memory data sheetTPCB_LAYOUT_SKEW50 50 50 Skew between layout lines on the boardTPHASE_OFFSET_ERROR140 140 140Offset between