1 Verilog Synthesis Examples CS/EE 3710 Fall 2010 Mostly from CMOS VLSI Design by Weste and Harris Behavioral Modeling  Using continuous assignments  ISE can build you a nice adder  Easier than specifying your own2 Bitwise Operators  Bitwise operations act on vectors (buses) More bitwise operators3 Reduction Operators  Apply operator to a single vector  Reduce to a single bit answer Conditional Operator  Classic mux  Can be confusing if you get crazy4 Using internal signals  Internal wires and regs can be used inside a module Using internal signals  Internal wires and regs can be used inside a module5 Operator Precedence Constants  Specified in binary, octal, decimal, or hex  Note use of underscore in long binary numbers6 Hierarchy  Instantiate other modules in your module Tristates  Assign the value z  Just say NO!  No on-board tri-states on Spartan3e FPGAs  Use MUXs instead!7 Bit Swizzling  Sometimes useful to work on part of a bus, or combine different signals together  Use bus (vector) notation Bit Swizzling  Sometimes useful to work on part of a bus, or combine different signals together  Use concatenation {} operator8 Registers  Edge-triggered flip flops  Always use reset of some sort! Registers  Can also add an enable signal  Only capture new data on clock and en9 Counters  Behavioral Counters  Structural10 Comb Logic with Always blocks  Always blocks are often sequential  But, if you have all RHS variables in the sensitivity list it can be combinational  Remember that you still must assign to a reg type Comb Logic with Always blocks  Always blocks are often sequential  But, if you have all RHS variables in the sensitivity list it can be combinational  Remember that you still must assign to a reg type11 Decoder example (combinational) Decoder example (combinational) Continuous assignment version is not as readable Same circuit though…12 Seven Segment Decoder Memories  Generally translates to block RAMs on the Spartan3e FPGA13 Shift Register? Blocking vs. Non-Blocking  Shift Register?14 Blocking vs. Non-Blocking  Shift Register? Finite State Machines  Divide into three sections  State register  Next state logic  output logic  Use parameters for state encodings15 Example  Three states, no inputs, one output, two state bits Example16 Mealy vs. Moore Mealy example Output is true if input is the same as it was on the last two cycles17 Mealy Example Parameterized Modules18 Verilog Style Guide  Use only non-blocking assignments in always blocks  Define combinational logic using assign statements whenever practical  Unless if or case makes things more readable  When modeling combinational logic with always blocks, if a signal is assigned in one branch of an if or case, it needs to be assigned in all branches Verilog Style Guide  Include default statements in your case statements  Use parameters to define state names and constants  Properly indent your code  Use comments liberally  Use meaningful variable names  Do NOT ignore synthesis warnings unless you know what they mean!19 Verilog Style Guide  Be very careful if you use both edges of the clock  It’s much safer to stick with one  I.e. @(posedge clock) only  Be certain not to imply latches  Watch for synthesis warnings about implied latches  Provide a reset on all registers Verilog Style Guide  Provide a common clock to all registers  Avoid gated clocks  Use enables