U of U CS 3710 - Compact RISC Processor (14 pages)

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Compact RISC Processor



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8 22 10 CS EE 3710 National Semiconductor CR16 Compact RISC Processor Baseline ISA and Beyond CR16 Architecture Part of a microcontroller family from National Semiconductor 16 bit embedded RISC processor core Available in Synethesizeable Verilog HDL Die size of 0 6 mm2 0 25 2 Mbytes of linear address space 221 Less than 0 2mA per MHZ 3 Volts 0 35 This has morphed into the CP3000 family University of Utah CS EE 3710 1 8 22 10 CR16 Architecture More specs Static 0 to 66 MHz clock frequency Direct bit manipulation instructions Save and Restore of Multiple Registers Push and Pop of Multiple Registers Hardware Multiplier Unit for fast 16 bit multiplication Interrupt and exception handling CS EE 3710 University of Utah CR16 Block Diagram University of Utah CS EE 3710 2 8 22 10 CR16 Register Set All registers are 16 bits wide Except address registers which are 21 bits Original version used 18 bits 16 general purpose registers 8 processor registers 3 dedicated address registers PC ISP INTBASE 1 Processor Status Register 1 configutation register 3 debug control registers CS EE 3710 University of Utah CR16 Registers University of Utah CS EE 3710 3 8 22 10 Processor Registers PSR Processor Status Register C T L F Z N E P I bits Carries conditions interrupt enables etc INTBASE Interrupt Base register Holds the address of the dispatch table for interrupts and traps ISP Interrupt Stack Pointer Points to the lowest address of the last item stored on the interrupt stack University of Utah CS EE 3710 CR16 Instruction Encoding More complex than our version University of Utah CS EE 3710 4 8 22 10 CR16 Instructions Most ALU instructions have two forms MOVi MOVW or MOVB Two address instruction formal One of the two arguments is also used as destination Rdest and is overwritten ADD R0 R3 R3 R0 R3 Little Endian data references Least significant is lowest numbered Both bits and bytes CS EE 3710 University of Utah CR16 Instructions University of Utah CS EE 3710 5 8 22 10 More CR16 Instructions University of Utah CS EE 3710 Even More CR16 Instructions University of Utah CS EE 3710 6 8 22 10 Still More CR16 Instructions University of Utah CS EE 3710 More and More Instructions University of Utah CS EE 3710 7 8 22 10 CR16 Memory Map CS EE 3710 University of Utah CR16 Exceptions Interrupt Exception caused by external activity CR16 recognizes three types Maskable Non maskable and ISE In System Emulator Trap Exception caused by program action Six types SVC DVZ FLG BPT TRC UND Interrupt process saves PC and PSR on interrupt stack RETX returns from interrupt University of Utah CS EE 3710 8 8 22 10 CR16 Pipeline Three stage pipe Fetch Decode Execute Instruction execution is serialized after an exception Also serialized after LPR RETX and EXCP CS EE 3710 University of Utah Our Class Version Baseline instruction set uses almost fixed instruction encoding Detailed description on the web page All instructions are a single 16 bit word All memory references inst or data operate on 16 bit words Not all instructions are included Each group will extend the baseline ISA somehow University of Utah CS EE 3710 9 8 22 10 Baseline ISA ADD ADDI SUB SUBI CMP CMPI AND ANDI OR ORI XOR XORI MOV MOVI LSH LSHI restricted to shift of one LUI LOAD STOR Bcond Jcond JAL CS EE 3710 University of Utah Class Encoding In the handout on the web Much more regular than real CR16 University of Utah CS EE 3710 10 8 22 10 Data Types All data is 16 bit Two s complement encoding for data Unsigned for address manipulation Boolean for boolean operations Of course the ALU doesn t know which is which they re all 16bit clumps to the ALU Flags are set for all interpretations The programmer can sort out the flags later CS EE 3710 University of Utah PSR Issues Only ADD ADDI SUB SUBI CMP CMPI can change the PSR flags CMP CMPI are the same as SUB SUBI But they affect the PSR differently Only PSR bits FLCNZ are needed for baseline implementation ADD ADDI SUB SUBI set the C on carry out and F on overflow CMP CMPI set Z L unsigned and N signed University of Utah CS EE 3710 11 8 22 10 Conditional Jumps Branches Jumps are absolute Branches are relative to current PC JAL Jump and Link stores the address of the next instruction in Rlink and jumps to Rtarget Return with JUC Rlink Conditions are derived from PSR bits CS EE 3710 University of Utah Condition Table University of Utah CS EE 3710 12 8 22 10 Memory Map 16 bit PC and LOAD STOR addresses 64k addresses Each address is a 16 bit word So 128k bytes of data but organized as words But only 40k bytes of block RAM on Spartan 3E 20k 16 bit words But 64M bytes of SDRAM But SDRAM is a pain We need to reserve some I O addresses Up to you but I recommend using the some top address bits Upper 16k words 32kbytes as I O space CS EE 3710 University of Utah Memory Map Word addresses FFFF C000 I O Switches LEDs UART LCD BFFF 8000 Code Data Top two address bits define regions 7FFF 4000 Code Data 3FFF Code Data University of Utah 0000 16k words 32k bytes CS EE 3710 13 8 22 10 Strata Flash 16 MByte 8 Mword flash ROM Designed to hold configuration data for the Spartan part But can be used for general non volatile data Memory Map Word addresses FFFF C000 I O Switches LEDs UART LCD BFFF Top two address bits define regions 8000 Flash ROM Code Data 3FFF Code Data University of Utah 0000 Glyphs Code SRAM Block RAM 7FFF 4000 Interrupt dispatch tables Frame buffer 4k additional words 16k words 32k bytes CS EE 3710 14


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