Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Verilog Synthesis ExamplesCS/EE 3710Fall 2008Mostly from CMOS VLSI Designby Weste and HarrisBehavioral ModelingUsing continuous assignmentsISE can build you a nice adderEasier than specifying your ownBitwise OperatorsBitwise operations act on vectors (buses)More bitwise operatorsReduction OperatorsApply operator to a single vectorReduce to a single bit answerConditional OperatorClassic muxCan be confusing if you get crazyUsing internal signalsInternal wires and regs can be used inside a moduleUsing internal signalsInternal wires and regs can be used inside a moduleOperator PrecedenceConstantsSpecified in binary, octal, decimal, or hexNote use of underscore in long binary numbersHierarchyInstantiate other modules in your moduleTristatesAssign the value zJust say NO! No on-board tri-states on Spartan3e FPGAsUse MUXs instead!Bit TwiddlingSometimes useful to work on part of a bus, or combine different signals togetherUse bus (vector) notationBit TwiddlingSometimes useful to work on part of a bus, or combine different signals togetherUse concatenation {} operatorRegistersEdge-triggered flip flopsAlways use reset of some sort!RegistersCan also add an enable signalOnly capture new data on clock and enCountersBehavioralCountersStructuralComb Logic with Always blocksAlways blocks are often sequentialBut, if you have all RHS variables in the sensitivity list it can be combinationalRemember that you still must assign to a reg typeComb Logic with Always blocksAlways blocks are often sequentialBut, if you have all RHS variables in the sensitivity list it can be combinationalRemember that you still must assign to a reg typeDecoder example (combinational)Decoder example (combinational)Continuous assignment versionis not as readableSame circuit though…Seven Segment DecoderMemoriesGenerally translates to block RAMs on the Spartan3e FPGAShift Register?Blocking vs. Non-BlockingShift Register?Blocking vs. Non-BlockingShift Register?Finite State MachinesDivide into three sectionsState registerNext state logicoutput logicUse parameters for state encodingsExampleThree states, no inputs, one output, two state bitsExampleMealy vs. MooreMealy exampleOutput is true ifinput is the same as it was on the last two cyclesMealy ExampleParameterized ModulesVerilog Style GuideUse only non-blocking assignments in always blocksDefine combinational logic using assign statements whenever practicalUnless if or case makes things more readableWhen modeling combinational logic with always blocks, if a signal is assigned in one branch of an if or case, it needs to be assigned in all branchesVerilog Style GuideInclude default statements in your case statementsUse parameters to define state names and constantsProperly indent your codeUse comments liberally Use meaningful variable namesDo NOT ignore synthesis warnings unless you know what they mean! (then document!)Verilog Style GuideBe very careful if you use both edges of the clockIt’s much safer to stick with one I.e. @(posedge clock) onlyBe certain not to imply latchesWatch for synthesis warnings about implied latchesProvide a reset on all registersVerilog Style GuideProvide a common clock to all registersAvoid gated clocksUse enables