Creating a SchematicTutorial: ISE 10.1i and the Spartan3e Board v1.0 This tutorial will show you how to: • Use a combination of schematics and Verilog to specify a design • Simulate that design • Define pin constraints for the FPGA (.ucf file) • Synthesize the design for the FPGA board • Generate a bit file • Load that bit file onto the Spartan3e board in your lab kit I assume that you’re using a DSL lab machine, or that you’ve installed Xilinx ISE 10.1i on your own machine. This tutorial is specifically for the Spartan3e board. The programming procedure is different than for the older Spartan2 boards from Xess. Setting up a New Project and specifying a circuit in Verilog 1. Start the ISE 10.1 tool from Xilinx. 2. Create a new project. The Create New Project wizard will prompt you for a location for your project. Note that by default this will be in the ISE folder the very first time you start up. You’ll probably want to change this to something in your own folder tree.3. On the second page of the Create New Project dialog, make sure that you use the Spartan3e Device Family, XC3S500 Device, FG320 Package, -5 Speed Grade. You can also specify HDL as the Top-Level Source Type with XST as the Synthesis Tool, ISE as the Simulator, and Verilog as the language. These aren’t critical, but they do save time later. 4. You can skip the other parts of the dialog, or you can use them to create new Verilog file templates for your project. I usually just skip them and create my own files later.5. Now you want to open a new source file. Use the Project►NewSource menu choice. This first one will be a Verilog file so make sure you’ve selected Verilog Module as the type and give it a name. I’m calling my example mynand. 6. When you press Next you’ll get a dialog box that lets you define the inputs and outputs of your new module. I’m adding two inputs (A and B), and one output named Y. Remember that Verilog is case sensitive!7. When you Finish, you’ll have a template for a Verilog module that you can fill in with your Verilog code. It looks like this (note that you can also fill in the spots in the comment header with more information):8. Now you can fill in the rest of the Verilog module to implement some Boolean function. I’ll implement a NAND for this example. You can use any of the Verilog techniques that you know about. (see the Brown & Vranesic text from 3700, for example, or any number of Verilog tutorials on the web.) Note that ISE 10.1 uses Verilog 2001 syntax where the inputs and outputs are defined right in the argument definition line. I’ll use a continuous assignment statement: assign Y = ~(A & B); as shown below, then I’ll save the file. 9. In order to use this Verilog code in a schematic, you’ll need to create a schematic symbol. Select the mynand.v file in the Sources window, then in the Processes window select Create Schematic Symbol under the Design Utilities. 10. You now have a piece of Verilog that you can simulate and synthesize as is, or you can also use it in a schematic as a component.Creating a Schematic Your project can be totally Verilog, or totally schematics, or a mixture of the two. This example will feature a mix, just to show you how it can be done. 1. Start by going to Project►NewSource and this time choosing schematic as the type. I’m calling this fulladd. You can probably guess where this is going… 2. In the schematic window you’ll see a frame in which you can put your schematic components. You can select components by selecting the Symbols tab in the Sources pane. The first one I like to add is under General Category and is the Title component for the schematic. You can fill in the fields of the Title by double clicking on it. Then I’ll add three copies of mynand from my example library, and two copies of the xor2 component from the Logic Category.3. Now I’ll use the wiring tool to connect up the components to make a Full Adder.4. I’ll use the I/O Marker tool to add markers on the signals that I’d like to export from this circuit. Double click on the I/O Markers to change their names The circuit with the I/O Marker looks like this:5. Save the schematic. You are now ready to simulate the circuit which consists of part schematics (using xor2 from the Xilinx library), and part Verilog (your mynand.v code). If you go back to the Sources pane and expand the fulladd schematic you will see that it includes three copies of mynand.v.Simulating your Circuit: Now that you have a saved source file (fulladd is the top file in this case), you can simulate its behavior. We’ll use the ISE simulator with a testbench to drive the simulation. Note that the testbench files that drive the simulations are also Verilog files. To simulate the fulladd circuit: 1. Go to the top left pane and change the Sources For: field to be Behavioral Simulation. This changes the view to include sources that are interesting for simulation, and also changes the options in the bottom Processes pane to show the simulation options. 2. You can go to the Project►NewSource menu again, or you can select Create New Source in the Processes pane. This will bring up the New Source Wizard. In that dialog type in the name of your testbench file, and make sure to select Verilog Test Fixture in the list on the left. I will name my testbench fulladd_tb (where the tb stands for testbench). The box looks like:3. The Next dialog asks you which source you want the testbench constructed from. I’ll choose fulladd, of course. The code that gets generated includes an instance of the fulladd schematic named UUT (for Unit Under Test).4. Note that the generated template has some code with an ‘ifdef for initializing things. I don’t use the ‘ifdef code. Instead I write my own initial block and driving code for testing the circuit. Remember that good testbenches ALWAYS use $display statements and “if” checks so that the testbench is self-checking! You could enumerate all 8eight possibilities of the inputs and check the outputs. I’m going to get a little tricky with a concatenation and a loop. 5. Once you fill in the testbench with Verilog code to drive the simulation, you can check the syntax and run the simulation from the Processes tab. The output will be displayed as waveforms, and the $display data will show up in the console as shown (after zooming out to see all the