U of U CS 3710 - Checkpoint 2 — Datapath Infrastructure

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CS/EE 3710 — Computer Architecture LabCheckpoint #2 — Datapath InfrastructureOverviewIn order to complete the datapath for your insert-name-here machine, the register file and ALU thatyou designed in checkpoint 1 needs a little support. In particular, the extra registers that were hinted at incheckpoint 1 need to be fleshed out and the initial memory interface needs to be completed. In order tohave a complete datapath, you need to make the program counter complete, the MAR (memory addressregister) and MDR (memory data register) need to be specified, the memory access process needs to befigured out (at least the initial version that uses block RAM on the FPGA), and other registers like theinstruction register and immediate register need to be instantiated, as well as sign extenders, etc. Oncethis is done, the remaining tasks are the instruction decoding, the control state machine, and (the biggie)figuring out what support you need for I/O for your application.Program CounterThe program counter is a dedicated special register in the machine that holds the address of the nextinstruction to execute. It needs to be capable of being updated in every way the PC needs to be updated.For your machine, this means that the PC needs to be incremented by one word (the normal case), addedto a (sign-extended) displacement (for branches) or loaded from a register (for jumps). Your datapathneeds to be able to perform all of these operations. If your PC is already set up to feed into your ALU,then you could do the branch displacement calculation by setting some input muxes so that the PC and theimmediate go to the ALU and the ALU function is set to add. You might load from a register by settingthe ALU such that the appropriate register source makes it through the ALU without modification. Thisvalue can then be latched into the PC. For the increment case, you could either put the PC through oneside of the ALU, and select a constant 1 for the other argument (put a constant value on one of the inputmuxes or something similar to that approach), or you could build your PC as a loadable counter. If you usethe counter approach you can load the counter for the update and displacement functions, and count thecounter for the increment-the-pc function. The choice is yours. The advantage of the counter is that youmay not have to use the complete datapath for each PC increment, the advantage of the increment-through-the-alu approach is that every pc-update function goes through the same process, but with different muxsettings. Remember that when you use the ALU to update the PC, you should not update the conditioncodes! Finally, remember that for a JAL instruction, the PC needs to have a path into the register file sothat PC+1 (i.e. the address of the next instruction following the JAL) can be stored in the link register.Your datapath must allow this operation.Another issue with the PC has to do with signed and unsigned arithmetic. Recall that the signedarithmetic is all done with two’s complement numbers. This means that the range of numbers in a 16-bitword is -32,768 to 32,767. On the other hand, if you use those 16 bits to encode an unsigned number, youcan represent 0 to 65,534 (64k). Since addresses are usually considered unsigned numbers, we need toconsider what it means to have an unsigned PC that is operated on by a two’s complement ALU, especiallyin the face of signed offsets that might require subtraction! Consider what happens if you try to use two’scomplement signed arithmetic to take a large unsigned number (large enough so the high-order-bit is 1)and add a negative signed number to it to try to subtract something (so the high-order bit is also onehere since it is a negative signed number). Does it work? Are there constraints on when it works? Irecommend trying this out on some smaller numbers to get a feel for what’s going on. Trying this on 4-or 5-bit numbers is a good way to test things out to make sure you understand what’s happening.Note that our PC is addressing 16-bit words and not bytes! I think the best way to think about it isthat with 16 bits of PC you can directly address 64k locations. Each of those locations is a 16-bit word. Ifyou really want to think about it as bytes then the address space (without playing any tricks with segmentregisters or things like that to increase the address space) is 128k bytes, and the PC 15:0 is the word-portion of that 17-bit byte-address-space. But that’s probably the wrong way to think about it. 64k wordsin the address space with each word being 16 bits is easier I think.Instruction RegisterThis is a 16-bit register that holds the current instruction that you are executing. From this registeryou can decode all the information needed to execute the instruction. This information will consist ofregister addresses (both sources and destinations), function code information for ALU and shifter, muxsettings for the various muxes in the control paths, and other information about which instruction is beingexecuted for so the control state machine knows what to do. The main issue with the instruction registeris where it gets its data from. See the MDR discussion for more details...Sign ExtensionVarious instructions in our machine make use of sign-extended immediate values. Recall from readingthe 3710-ISA handout that immediate values in arithmetic operations are sign-extended from the 8-bitsthat are in the instruction encoding. Logical immediate operations are zero-extended instead of sign-extended. Check the 3710-ISA handout for details. Sign extension can be easily done using Verilogconcatenations as inputs to various circuit components like muxes.Memory and Memory-Mapped I/O SystemLoad and Store instructions on our version of the machine also point to word locations just like thePC (load and store addresses are word-addresses). There’s no way to load a single byte on our machine.Thus, the Load and Store instructions also use word addresses. In this machine I/O is memory-mappedwhich means that access to I/O devices is by loading and storing to special locations in the memory space.Each of those locations will be a 16-bit location because all loads and stores deal with 16-bit data in ourmachine.The memory map for one example of our baseline machine is shown in the slides on the web page(last slide in the CR-16 intro slides). In that case the memory was separated into four equal sized chunks.These chunks are either 16k words if you’re


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