1Mini-MIPSFrom Weste/Harris CMOS VLSI DesignCS/EE 3710Based on MIPS In fact, it’s based on the multi-cycle MIPS from Patterson and Hennessy Your CS/EE 3810 book... 8-bit version 8-bit data and address 32-bit instruction format 8 registers numbered $0-$7z $0 is hardwired to the value 0CS/EE 3710Instruction SetCS/EE 3710Instruction EncodingCS/EE 3710Fibonacci C-CodeCS/EE 3710Fibonacci C-CodeCycle 1: f1 = 1 + (-1) = 0, f2 = 0 – (-1) = 1Cycle 2: f1 = 0 + 1 = 1, f2 = 1 – 1 = 0Cycle 3: f1 = 1 + 0 = 1, f2 = 1 – 0 = 1Cycle 4: f1 = 1 + 1 = 2, f2 = 2 – 1 = 1Cycle 5: f1 = 2 + 1 = 3, f2 = 3 – 1 = 2Cycle 6: f1 = 3 + 2 = 5, f2 = 5 – 2 = 32CS/EE 3710Fibonacci Assembly CodeCompute 8thFibonacci number (8’d13 or 8’h0D)Store that number in memory location 255CS/EE 3710Fibonacci Machine Code 1010004Assembly CodeMachine CodeCS/EE 3710ArchitectureCS/EE 3710ArchitectureCS/EE 3710Another ViewCS/EE 3710Control FSM3CS/EE 3710Connection to External MemoryCS/EE 3710External Memory from Book// external memory accessed by MIPSmodule exmemory #(parameter WIDTH = 8)(input clk,input memwrite,input [WIDTH-1:0] adr, writedata,output reg [WIDTH-1:0] memdata);reg [31:0] RAM [(1<<WIDTH-2)-1:0];wire [31:0] word;// Initialize memory with programinitial $readmemh("memfile.dat",RAM);// read and write bytes from 32-bit wordalways @(posedge clk)if(memwrite) case (adr[1:0])2'b00: RAM[adr>>2][7:0] <= writedata;2'b01: RAM[adr>>2][15:8] <= writedata;2'b10: RAM[adr>>2][23:16] <= writedata;2'b11: RAM[adr>>2][31:24] <= writedata;endcaseassign word = RAM[adr>>2];always @(*)case (adr[1:0])2'b00: memdata <= word[7:0];2'b01: memdata <= word[15:8];2'b10: memdata <= word[23:16];2'b11: memdata <= word[31:24];endcaseendmoduleNotes: • Endianess is fixed here• Writes are on posedge clk• Reads are asynchronous• This is a 32-bit wide RAM• With 64 locations• But with an 8-bit interface... CS/EE 3710Exmem.v module exmem #(parameter WIDTH = 8, RAM_ADDR_BITS = 8)(input clk, en,input memwrite,input [RAM_ADDR_BITS-1:0] adr,input [WIDTH-1:0] writedata,output reg [WIDTH-1:0] memdata);reg [WIDTH-1:0] mips_ram [(2**RAM_ADDR_BITS)-1:0];initial $readmemb("fib.dat", mips_ram);always @(posedge clk)if (en) beginif (memwrite)mips_ram[adr] <= writedata;memdata <= mips_ram[adr];endendmodule•This is synthesized toa Block RAM on the Spartan3e FPGA• It’s 8-bits wide• With 256 locations• Both writes and reads are clockedCS/EE 3710Exmem.vmodule exmem #(parameter WIDTH = 8, RAM_ADDR_BITS = 8)(input clk, en,input memwrite,input [RAM_ADDR_BITS-1:0] adr,input [WIDTH-1:0] writedata,output reg [WIDTH-1:0] memdata);reg [WIDTH-1:0] mips_ram [(2**RAM_ADDR_BITS)-1:0];initial $readmemb("fib.dat", mips_ram);always @(posedge clk)if (en) beginif (memwrite)mips_ram[adr] <= writedata;memdata <= mips_ram[adr];endendmoduleThis is synthesized toa Block RAM on the Spartan3e FPGANote clock!CS/EE 3710Block RAMByte-wide Block RAM isreally 9-bits – parity bit... (Actually dual ported too!)CS/EE 3710Our Block Ram Read-first or Write-first? always @(posedge clk)if (en) beginif (memwrite)mips_ram[adr] <= writedata;memdata <= mips_ram[adr];end4CS/EE 3710Read_First TemplateCS/EE 3710Write_First TemplateCS/EE 3710Read_First waveformsCS/EE 3710Write_First WaveformsCS/EE 3710Block RAM OrganizationEach block is18k bits... Block RAM is Single or DualportedCS/EE 3710Recall – Overall SystemClockClkClk5CS/EE 3710Recall – Overall SystemClockClkClkSo, what are the implications of using a RAM that has both clocked reads and writes instead of clocked writes and async reads? (we’ll come back to this question...)CS/EE 3710mips Block DiagramCS/EE 3710mips.v// simplified MIPS processormodule mips #(parameter WIDTH = 8, REGBITS = 3)(input clk, reset, input [WIDTH-1:0] memdata, output memread, memwrite, output [WIDTH-1:0] adr, writedata);wire [31:0] instr;wire zero, alusrca, memtoreg, iord, pcen, regwrite, regdst;wire [1:0] aluop,pcsource,alusrcb;wire [3:0] irwrite;wire [2:0] alucont;controller cont(clk, reset, instr[31:26], zero, memread, memwrite,alusrca, memtoreg, iord, pcen, regwrite, regdst,pcsource, alusrcb, aluop, irwrite);alucontrol ac(aluop, instr[5:0], alucont);datapath #(WIDTH, REGBITS)dp(clk, reset, memdata, alusrca, memtoreg, iord, pcen,regwrite, regdst, pcsource, alusrcb, irwrite, alucont,zero, instr, adr, writedata);endmoduleCS/EE 3710ControllerState CodesUseful constants to compare againstState RegisterCS/EE 3710Control FSMCS/EE 3710Next State Logic6CS/EE 3710Output LogicContinued for the other states... Very common wayto deal with defaultvalues in combinationalAlways blocksCS/EE 3710Output LogicWhy AND these two? Two places to update the PCpcwrite on jumppcwritecond on BEQCS/EE 3710ALU ControlCS/EE 3710ALUInvert b if subtract... add is a + bsub is a + ~b +1subtract on sltthen check if answer is negativeCS/EE 3710zerodetectCS/EE 3710Register FileWhat is this synthesizedinto?7CS/EE 3710Synthesis ReportCS/EE 3710Synthesis ReportCS/EE 3710Synthesis ReportTwo registerfiles? Why? CS/EE 3710DatapathFairly complex... Not really, but it doeshave lots of registersinstantiated directlyIt also instantiates muxes... Instruction RegisterCS/EE 3710Datapath continuedFlops andmuxes... RF and ALUCS/EE 3710Flops and MUXes8CS/EE 3710Back to the Memory Question What are the implications of using RAM that is clocked on both write and read? Book version was async read So, let’s look at the sequence of events that happen to read the instruction Four steps – read four bytes and put them in four slots in the 32-bit instruction register (IR) CS/EE 3710Instruction FetchCS/EE 3710Instruction FetchCS/EE 3710Instruction Fetch• Memread, irwrite, addr, etc are set up just after clk edge• Data comes back sometime after that (async)• Data is captured in ir0 – ir3 on the next rising clk edge• How does this change if reads are clocked?CS/EE 3710mips + exmemOne of those rare cases where using both edges of the clock is useful! mips is expecting async reads exmem has clocked readsCS/EE 3710Memory Mapped I/O Break memory space into pieces (ranges) For some of those pieces: regular memory For some of those pieces: I/Oz That is, reading from an address in that range results in getting data from an I/O devicez Writing to an address in that range results in data going to an I/O device9CS/EE 3710Mini-MIPS Memory MapI/OSwitches/LEDsCode/DataCode/DataCode/Data003F407F80BFC0FF64 bytesTop two addressbits
View Full Document