Administrivia Homework 4 due in 1 week April 14 Exam 2 pushed back to April 21 Cache simulator project posted due May 1 CMSC 411 Computer Systems Architecture Lecture 16 Virtual Memory CSIC Linuxlab account info handed out today Start reading Ch 6 not 6 5 400 level lecture series today and tomorrow CSIC 2117 at 5PM sponsored p by y AWC Alan Sussman als cs umd edu l d d CMSC 411 16 some from Patterson Sussman others Two Level Page Tables Choosing page size A large page size Each process needs its own address space keeps page table small reduces cache miss times if accesses have locality reduces start up overhead in moving data from disk to memory means fewer f TLB misses i Two level Page Tables but also 32 bit virtual address 31 2 wastes memory internal fragmentation increases the time to start up a program 22 21 12 11 0 P1 index P2 index Page Offset Top level table wired in main memory Subset of 1024 second level tables in main memory rest are on disk or unallocated ll t d CMSC 411 16 some from Patterson Sussman others 3 CMSC 411 16 some from Patterson Sussman others 4 VM and Disk Page replacement policy MIPS Address Translation How does it work Page g Table Dirty bit page written 1 1 U d bit Used bit sett to t 0 1 on any 1 reference 0 Set of all pages in Memory 0 0 1 1 0 Virtual A0 A31 0 3 Physical A0 A31 A0 A31 Translation Look Aside Buffer TLB CPU D0 D31 Memory D0 D31 Data Tail pointer Clear the used bit in the page table Translation Look Aside Look Aside Buffer TLB A small fully associative cache of mappings from virtual to physical addresses Freelist Head pointer Place pages on free list if used bit is still clear Schedule pages with dirty bit set to be written to disk Physical Addresses Virtual Addresses dirty used TLB also contains protection bits for virtual address Hardware Architect s role support setting dirty and used bits Free Pages Fast common case case Virt Virtual al address is in TLB TLB process has permission to read write it 5 CMSC 411 16 some from Patterson Sussman others The TLB caches page table entries 6 CMSC 411 16 some from Patterson Sussman others Common Organization Physical and virtual pages must be the same size virtual address page CPU Physical frame address off ff TLB Page Table Even a cache hit requires TLB translation first L1 Cache 2 Write Buffer 0 L2 Cache 1 3 physical address TLB frame 2 0 page 2 5 page off MIPS handles TLB misses in software random replacement Other machines use hardware CMSC 411 16 some from Patterson Sussman others V 0 pages either reside on disk or have not yet been allocated ll t d OS handles V 0 Page fault 7 Memory bus CMSC 411 16 some from Patterson Sussman others 8 Problems With Overlapped TLB Access Can TLB and caching be overlapped Virtual Page Number Overlapped access only works as long as the address bits used to g as the result off VA translation index into the cache do not change This usually limits things to small caches large page sizes or high n way set associative caches if you want a large cache Page Offset Index Byte Select Example E l suppose everything h the h same except that h the h cache h is increased to 8 K bytes instead of 4 K Virtual Translation Look Aside Look Aside Buffer TLB Cache Tags g Valid 11 Cache Data cache index Cache Block Physical Cache Tag This works works but A Inflexibility Size of cache limited by page size Data out Use virtual addresses for cache Virtual D0 D31 D0 D31 1K 4 2 way set assoc cache 4 10 CMSC 411 16 some from Patterson Sussman others Paging g g vs segmentation g Fig g C 21 Physical Addresses Virtual Cache 10 9 CMSC 411 16 some from Patterson Sussman others CPU 12 disp This bit is changed by VA translation but i needed is d d f for cache h lookup Solutions go to 8K byte page sizes go to 2 way set associative cache or SW guarantee VA 13 PA 13 Hit Virtual Addresses 20 virt page Cache Block Q What is the downside A0 A31 2 00 Physical y Translation Look Aside Buffer TLB Segment Main Memory Words per address One Two segment offset D0 D31 Programmer visible Invisible to app programmer May be visible to app programmer R l i a bl Replacing block k T i i l allll bl Trivial blocks k same size i Hard must find contiguous variable sized chunk Memory use inefficiency Internal fragmentation within page External fragmentation in unused memory Efficient disk traffic Yes can adjust page size Not always small segment problem O Only use TLB on a cache miss Downside a subtle fatal problem p What is it A Synonym problem If two address spaces share a physical frame frame data may be in cache twice twice Maintaining consistency is a nightmare CMSC 411 16 some from Patterson Sussman others Page A0 A31 11 CMSC 411 16 some from Patterson Sussman others 12 Summary 1 3 The Cache Design Space Summary 2 3 Caches Cache Size Several interacting dimensions cache size block size associativity replacement policy write through vs write back write through write back write allocation A Associativity i ti it Program accesses a relatively small portion of the address space in any short interval of time Temporal Locality Locality in Time Spatial Locality Locality in Space Three Major Categories of Cache Misses The optimal choice is a compromise depends on access characteristics workload use I cache D cache TLB depends on technology cost Simplicity often wins The Principle of Locality Compulsory Misses sad facts of life Example cold start misses Capacity Misses increase cache size Conflict Misses increase cache size and or associativity Nightmare Scenario ping pong effect Block Size Bad Good Factor A Less Factor B More CMSC 411 16 some from Patterson Sussman others 13 Summary 3 3 TLB Virtual Memory Page tables map virtual address to physical address TLBs are important for fast translation TLB misses are significant in processor performance funny times as most systems can t access all of 2nd level cache without TLB misses Caches TLBs Virtual Memory all understood by examining how they deal with 4 questions 1 Where can block be p placed 2 How is block found 3 What block is replaced on miss 4 How are writes handled Today VM allows many processes to share single memory without having to swap all processes to disk today VM protection is maybe even more important than memory hierarchy benefits but computers still insecure CMSC 411 16 some from Patterson Sussman others Write Policy Write Through vs Write Back Today CPU time is a function of ops cache misses vs just j t f ops f affects ff t C Compilers il Data D t